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PIC24FJ256GB110 Family Data Sheet
64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)
(c) 2008 Microchip Technology Inc.
Preliminary
DS39897B
Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS39897B-page ii
Preliminary
(c) 2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)
Power Management:
* On-Chip 2.5V Voltage Regulator * Switch between Clock Sources in Real Time * Idle, Sleep and Doze modes with Fast Wake-up and Two-Speed Start-up * Run mode: 1 mA/MIPS, 2.0V Typical * Sleep mode Current Down to 100 nA Typical * Standby Current with 32 kHz Oscillator: 2.5 A, 2.0V typical
High-Performance CPU:
* * * * * * * Modified Harvard Architecture Up to 16 MIPS Operation at 32 MHz 8 MHz Internal Oscillator 17-Bit x 17-Bit Single-Cycle Hardware Multiplier 32-Bit by 16-Bit Hardware Divider 16 x 16-Bit Working Register Array C Compiler Optimized Instruction Set Architecture with Flexible Addressing modes * Linear Program Memory Addressing, Up to 12 Mbytes * Linear Data Memory Addressing, Up to 64 Kbytes * Two Address Generation Units for Separate Read and Write Addressing of Data Memory
Universal Serial Bus Features:
* USB v2.0 On-The-Go (OTG) Compliant * Dual Role Capable - can act as either Host or Peripheral * Low-Speed (1.5 Mb/s) and Full-Speed (12 Mb/s) USB Operation in Host mode * Full-Speed USB Operation in Device mode * High-Precision PLL for USB * Internal Voltage Boost Assist for USB Bus Voltage Generation * Interface for Off-Chip Charge Pump for USB Bus Voltage Generation * Supports up to 32 Endpoints (16 bidirectional): - USB Module can use any RAM location on the device as USB endpoint buffers * On-Chip USB Transceiver with On-Chip Voltage Regulator * Interface for Off-Chip USB Transceiver * Supports Control, Interrupt, Isochronous and Bulk Transfers * On-Chip Pull-up and Pull-Down Resistors
Analog Features:
* 10-Bit, Up to 16-Channel Analog-to-Digital (A/D) Converter at 500 ksps: - Conversions available in Sleep mode * Three Analog Comparators with Programmable Input/ Output Configuration * Charge Time Measurement Unit (CTMU)
Program Memory (Bytes)
10-Bit A/D (ch)
SRAM (Bytes)
Remappable Peripherals UART w/IrDA(R) Capture Input Timers 16-Bit Compare/ PWM Output Remappable Pins I2CTM
Comparators
PMP/PSP
PIC24FJ64GB106 PIC24FJ128GB106 PIC24FJ192GB106 PIC24FJ256GB106 PIC24FJ64GB108 PIC24FJ128GB108 PIC24FJ192GB108 PIC24FJ256GB108 PIC24FJ64GB110 PIC24FJ128GB110 PIC24FJ192GB110 PIC24FJ256GB110
64 64 64 64 80 80 80 80 100 100 100 100
64K 128K 192K 256K 64K 128K 192K 256K 64K 128K 192K 256K
16K 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K
29 29 29 29 40 40 40 40 44 44 44 44
5 5 5 5 5 5 5 5 5 5 5 5
9 9 9 9 9 9 9 9 9 9 9 9
9 9 9 9 9 9 9 9 9 9 9 9
4 4 4 4 4 4 4 4 4 4 4 4
SPI
Device
3 3 3 3 3 3 3 3 3 3 3 3
3 3 3 3 3 3 3 3 3 3 3 3
16 16 16 16 16 16 16 16 16 16 16 16
3 3 3 3 3 3 3 3 3 3 3 3
Y Y Y Y Y Y Y Y Y Y Y Y
Y Y Y Y Y Y Y Y Y Y Y Y
Y Y Y Y Y Y Y Y Y Y Y Y
(c) 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 1
USBOTG Y Y Y Y Y Y Y Y Y Y Y Y
CTMU
JTAG
Pins
PIC24FJ256GB110 FAMILY
Peripheral Features:
* Peripheral Pin Select: - Allows independent I/O mapping of many peripherals at run time - Continuous hardware integrity checking and safety interlocks prevent unintentional configuration changes - Up to 44 available pins (100-pin devices) * Three 3-Wire/4-Wire SPI modules (supports 4 Frame modes) with 8-Level FIFO Buffer * Three I2CTM modules support Multi-Master/Slave modes and 7-Bit/10-Bit Addressing * Four UART modules: - Supports RS-485, RS-232, LIN/J6202 protocols and IrDA(R) - On-chip hardware encoder/decoder for IrDA - Auto-wake-up and Auto-Baud Detect (ABD) - 4-level deep FIFO buffer * Five 16-Bit Timers/Counters with Programmable Prescaler * Nine 16-Bit Capture Inputs, each with a Dedicated Time Base * Nine 16-Bit Compare/PWM Outputs, each with a Dedicated Time Base * 8-Bit Parallel Master Port (PMP/PSP): - Up to 16 address pins - Programmable polarity on control lines * Hardware Real-Time Clock/Calendar (RTCC): - Provides clock, calendar and alarm functions * Programmable Cyclic Redundancy Check (CRC) Generator * Up to 5 External Interrupt Sources
Special Microcontroller Features:
* * * * * * * Operating Voltage Range of 2.0V to 3.6V Self-Reprogrammable under Software Control 5.5V Tolerant Input (digital pins only) Configurable Open-Drain Outputs on Digital I/O High-Current Sink/Source (18 mA/18 mA) on all I/O Selectable Power Management modes: - Sleep, Idle and Doze modes with fast wake-up Fail-Safe Clock Monitor Operation: - Detects clock failure and switches to on-chip, low-power RC oscillator On-Chip LDO Regulator Power-on Reset (POR), Power-up Timer (PWRT), Low-Voltage Detect (LVD) and Oscillator Start-up Timer (OST) Flexible Watchdog Timer (WDT) with On-Chip. Low-Power RC Oscillator for Reliable Operation In-Circuit Serial ProgrammingTM (ICSPTM) and In-Circuit Debug (ICD) via 2 Pins JTAG Boundary Scan and Programming Support Brown-out Reset (BOR) Flash Program Memory: - 10,000 erase/write cycle endurance (minimum) - 20-year data retention minimum - Selectable write protection boundary - Write protection option for Flash Configuration Words
* *
* * * * *
DS39897B-page 2
Preliminary
(c) 2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
Pin Diagram (64-Pin TQFP)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PMD4/CN62/RE4 PMD3/CN61/RE3 PMD2/CN60/RE2 PMD1/CN59/RE1 PMD0/CN58/RE0 VCMPST2/CN69/RF1 VBUSST/VCMPST1/CN68/RF0 ENVREG VCAP/VDDCORE C3INA/CN16/RD7 C3INB/CN15/RD6 PMRD/RP20/CN14/RD5 PMWR/RP25/CN13/RD4 RP22/PMBE/CN52/RD3 DPH/RP23/CN51/RD2 RP24/VCPCON/CN50/RD1
PMD5/CN63/RE5 PMD6/SCL3/CN64/RE6 PMD7/SDA3/CN65/RE7 PMA5/RP21/C1IND/CN8/RG6 RP26/PMA4/C1INC/CN9/RG7 PMA3/RP19/C2IND/CN10/RG8 MCLR RP27/PMA2/C2INC/CN11/RG9 VSS VDD PGEC3/RP18/VBUSON/C1INA/AN5/CN7/RB5 PGED3/RP28/USBOEN/C1INB/AN4/CN6/RB4 VPIO/C2INA/AN3/CN5/RB3 VMIO/RP13/C2INB/AN2/CN4/RB2 PGEC1/RP1/VREF-/AN1/CN3/RB1 PGED1/RP0/PMA6/VREF+/AN0/CN2/RB0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
RPI37/SOSCO/C3INC/TICK/ CN0/RC14 SOSCI/C3IND/CN1/RC13 RP11/DMH/CN49/INT0/RD0 RP12/PMCS1/CN56/RD11 RP3/SCL1/PMCS2/CN55/RD10 RP4/DPLN/SDA1/CN54/RD9 RP2/DMLN/RTCC/CN53/RD8 VSS OSCO/CLKO/CN22/RC15 OSCI/CLKI/CN23/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS RP16/USBID/CN71/RF3
PIC24FJXXXGB106
Legend:
RPn represents remappable pins for Peripheral Pin Select feature.
(c) 2008 Microchip Technology Inc.
Preliminary
TCK/PMA11/AN12/CTED2/CN30/RB12 TDI/PMA10/AN13/CTED1/CN31/RB13 CTPLS/RP14/PMA1/AN14/CN32/RB14 RP29/PMA0/AN15/REFO/CN12/RB15 PMA9/RP10/SDA2/CN17/RF4 PMA8/RP17/SCL2/CN18/RF5
PGEC2/AN6/RP6/CN24/RB6 PGED2/RCV/RP7/AN7/CN25/RB7 AVDD AVSS RP8/AN8/CN26/RB8 PMA7/RP9/AN9/CN27/RB9 TMS/PMA13/AN10/CVREF/CN28/RB10 TDO/AN11/PMA12/CN29/RB11 VSS VDD
DS39897B-page 3
PIC24FJ256GB110 FAMILY
Pin Diagram (80-Pin TQFP)
PMD1/CN59/RE1 PMD0/CN58/RE0 CN77/RG0 CN78/RG1 VCMPST2/CN69/RF1 VBUSST/VCMPST1/CN68/RF0
80 79 78 77 76
75 74 73 72 71 70 69 68 67 66
65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
PMRD/RP20/CN14/RD5 PMWR/RP25/CN13/RD4 CN19/RD13 RPI42/CN57/RD12
VCAP/VDDCORE C3INA/CN16/RD7 C3INB/CN15/RD6
RP22/PMBE/CN52/RD3 DPH/RP23/CN51/RD2 RP24/VCPCON/CN50/RD1
PMD4/CN62/RE4 PMD3/CN61/RE3
PMD2/CN60/RE2
ENVREG
PMD5/CN63/RE5 PMD6/SCL3/CN64/RE6 PMD7/SDA3/CN65/RE7 RPI38/CN45/RC1 RPI40/CN47/RC3 PMA5/RP21/C1IND/CN8/RG6 RP26/PMA4/C1INC/CN9/RG7 PMA3/RP19/C2IND/CN10/RG8 MCLR RP27/PMA2/C2INC/CN11/RG9 VSS VDD TMS/RPI33/CN66/RE8 TDO/RPI34/CN67/RE9 PGEC3/RP18/VBUSON/C1INA/AN5/CN7/RB5 PGED3/RP28/USBOEN/C1INB/AN4/CN6/RB4 VPIO/C2INA/AN3/CN5/RB3 VMIO/RP13/C2INB/AN2/CN4/RB2 PGEC1/RP1/AN1/CN3/RB1 PGED1/RP0/AN0/CN2/RB0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
RPI37/SOSCO/C3INC/T1CK/CN0/RC14 SOSCI/C3IND/CN1/RC13 RP11/DMH/CN49/INT0/RD0 RP12/PMCS1/CN56/RD11 RP3/PMCS2/SCL1/CN55/RD10 RP4/DPLN/SDA1/CN54/RD9 RP2/DMLN/RTCC/CN53/RD8 RPI35/SDA2/CN44/RA15 RPI36/SCL2/CN43/RA14 VSS OSCO/CLKO/CN22/RC15 OSCI/CLKI/CN23/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS RP15/CN74/RF8 RP30/CN70/RF2 RP16/USBID/CN71/RF3
PIC24FJXXXGB108
PGED2/RCV/RP7/AN7/CN25/RB7
AN11/PMA12/CN29/RB11 Vss
AVSS RP8/AN8/CN26/RB8
RP9/AN9/CN27/RB9
RP5/CN21/RD15
AVDD
VDD
RP10/PMA9/CN17/RF4
PMA6/VREF+/CN42/RA10
TCK/AN12/CTED2/PMA11/CN30/RB12
TDI/AN13/CTED1/PMA10/CN31/RB13
Legend:
RPn and RPIn represent remappable pins for Peripheral Pin Select feature.
DS39897B-page 4
Preliminary
CTPLS/RP14/PMA1/AN14/CN32/RB14
RP29/PMA0/AN15/REFO/CN12/RB15 RPI43/CN20/RD14
PGEC2/AN6/RP6/CN24/RB6
PMA7/VREF-/CN41/RA9
AN10/CVREF/PMA13/CN28/RB10
RP17/PMA8/CN18/RF5
(c) 2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
Pin Diagram (100-Pin TQFP)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PMD2/CN60/RE2 CN80/RG13 CN79/RG12 CN81/RG14 PMD1/CN59/RE1 PMD0/CN58/RE0 CN40/RA7 CN39/RA6 CN77/RG0 CN78/RG1 VCMPST2/CN69/RF1 VBUSST/VCMPST1/CN68/RF0 ENVREG VCAP/VDDCORE C3INA/CN16/RD7 C3INB/CN15/RD6 PMRD/RP20/CN14/RD5 PMWR/RP25/CN13/RD4 CN19/RD13 RPI42/CN57/RD12 RP22/PMBE/CN52/RD3 DPH/RP23/CN51/RD2 RP24/VCPCON/CN50/RD1
PMD4/CN62/RE4 PMD3/CN61/RE3
CN82/RG15 VDD PMD5/CN63/RE5 PMD6/SCL3/CN64/RE6 PMD7/SDA3/CN65/RE7 RPI38/CN45/RC1 RPI39/CN46/RC2 RPI40/CN47/RC3 RPI41/CN48/RC4 PMA5/RP21/C1IND/CN8/RG6 RP26/PMA4/C1INC/CN9/RG7 RP19/PMA3/C2IND/CN10/RG8 MCLR RP27/PMA2/C2INC/CN11/RG9 VSS VDD TMS/CN33/RA0 RPI33/CN66/RE8 RPI34/CN67/RE9 PGEC3/RP18/VBUSON/C1INA/AN5/CN7/RB5 PGED3/RP28/USBOEN/C1INB/AN4/CN6/RB4 VPIO/C2INA/AN3/CN5/RB3 VMIO/RP13/C2INB/AN2/CN4/RB2 PGEC1/RP1/AN1/CN3/RB1 PGED1/RP0/AN0/CN2/RB0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65
VSS RPI37/SOSCO/C3INC/T1CK/ CN0/RC14 SOSCI/C3IND/CN1/RC13 RP11/DMH/CN49/INT0/RD0 RP12/PMCS1/CN56/RD11 RP3/PMCS2/CN55/RD10 RP4/DPLN/CN54/RD9 RP2/DMLN/RTCC/CN53/RD8 RPI35/SDA1/CN44/RA15 RPI36/SCL1/CN43/RA14 VSS OSCO/CLKO/CN22/RC15 OSCI/CLKI/CN23/RC12 VDD TDO/CN38/RA5 TDI/CN37/RA4 SDA2/CN36/RA3 SCL2/CN35/RA2 D+/RG2 D-/RG3 VUSB VBUS RP15/CN74/RF8 RP30/CN70/RF2 RP16/USBID/CN71/RF3
PIC24FJXXXGB110
64 63 62 61 60 59 58 57 56 55 54 53 52 51
AN11/PMA12/CN29/RB11 VSS VDD TCK/CN34/RA1 RP31/CN76/RF13 RPI32/CN75/RF12 AN12/CTED2/PMA11/CN30/RB12 AN13/CTED1/PMA10/CN31/RB13 CTPLS/RP14/PMA1/AN14/CN32/RB14 RP29/PMA0/AN15/REFO/CN12/RB15
Legend:
RPn and RPIn represent remappable pins for Peripheral Pin Select feature.
(c) 2008 Microchip Technology Inc.
PGEC2/AN6/RP6/CN24/RB6 PGED2/RCV/RP7/AN7/CN25/RB7 PMA7/VREF-/CN41/RA9 PMA6/VREF+/CN42/RA10 AVDD AVSS RP8/AN8/CN26/RB8 RP9/AN9/CN27/RB9 AN10/CVREF/PMA13/CN28/RB10
Preliminary
VSS VDD RPI43/CN20/RD14 RP5/CN21/RD15 RP10/PMA9/CN17/RF4 RP17/PMA8/CN18/RF5
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DS39897B-page 5
PIC24FJ256GB110 FAMILY
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9 2.0 CPU ........................................................................................................................................................................................... 25 3.0 Memory Organization ................................................................................................................................................................. 31 4.0 Flash Program Memory .............................................................................................................................................................. 55 5.0 Resets ........................................................................................................................................................................................ 61 6.0 Interrupt Controller ..................................................................................................................................................................... 67 7.0 Oscillator Configuration ............................................................................................................................................................ 109 8.0 Power-Saving Features ............................................................................................................................................................ 119 9.0 I/O Ports ................................................................................................................................................................................... 121 10.0 Timer1 ...................................................................................................................................................................................... 147 11.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 149 12.0 Input Capture with Dedicated Timers ....................................................................................................................................... 155 13.0 Output Compare with Dedicated Timers .................................................................................................................................. 159 14.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 169 15.0 Inter-Integrated Circuit (I2CTM) ................................................................................................................................................. 179 16.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 187 17.0 Universal Serial Bus with On-The-Go Support (USB OTG) ..................................................................................................... 195 18.0 Parallel Master Port (PMP)....................................................................................................................................................... 225 19.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 235 20.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 245 21.0 10-bit High-Speed A/D Converter............................................................................................................................................. 249 22.0 Triple Comparator Module........................................................................................................................................................ 259 23.0 Comparator Voltage Reference................................................................................................................................................ 263 24.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 265 25.0 Special Features ...................................................................................................................................................................... 269 26.0 Development Support............................................................................................................................................................... 281 27.0 Instruction Set Summary .......................................................................................................................................................... 285 28.0 Electrical Characteristics .......................................................................................................................................................... 293 29.0 Packaging Information.............................................................................................................................................................. 307 Appendix A: Revision History............................................................................................................................................................. 317 Index ................................................................................................................................................................................................. 319 The Microchip Web Site ..................................................................................................................................................................... 323 Customer Change Notification Service .............................................................................................................................................. 323 Customer Support .............................................................................................................................................................................. 323 Reader Response .............................................................................................................................................................................. 324 Product Identification System............................................................................................................................................................. 325
DS39897B-page 6
Preliminary
(c) 2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.
Most Current Data Sheet
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using.
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(c) 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 7
PIC24FJ256GB110 FAMILY
NOTES:
DS39897B-page 8
Preliminary
(c) 2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
1.0 DEVICE OVERVIEW
This document contains device-specific information for the following devices: * PIC24FJ64GB106 * PIC24FJ128GB106 * PIC24FJ192GB106 * PIC24FJ256GB106 * PIC24FJ64GB108 * PIC24FJ128GB108 * PIC24FJ192GB108 * PIC24FJ256GB108 * PIC24FJ64GB110 * PIC24FJ128GB110 * PIC24FJ192GB110 * PIC24FJ256GB110 * Doze Mode Operation: When timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the CPU clock speed can be selectively reduced, allowing incremental power savings without missing a beat. * Instruction-Based Power-Saving Modes: The microcontroller can suspend all operations, or selectively shut down its core while leaving its peripherals active, with a single instruction in software.
1.1.3
This expands on the existing line of Microchip`s 16-bit microcontrollers, combining an expanded peripheral feature set and enhanced computational performance with a new connectivity option: USB On-The-Go. The PIC24FJ256GB110 family provides a new platform for high-performance USB applications which may need more than an 8-bit platform, but don't require the power of a digital signal processor.
OSCILLATOR OPTIONS AND FEATURES
All of the devices in the PIC24FJ256GB110 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: * Two Crystal modes using crystals or ceramic resonators. * Two External Clock modes offering the option of a divide-by-2 clock output. * A Fast Internal Oscillator (FRC) with a nominal 8 MHz output, which can also be divided under software control to provide clock speeds as low as 31 kHz. * A Phase Lock Loop (PLL) frequency multiplier, available to the external oscillator modes and the FRC oscillator, which allows clock speeds of up to 32 MHz. * A separate internal RC oscillator (LPRC) with a fixed 31 kHz output, which provides a low-power option for timing-insensitive applications. The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor. This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown.
1.1
1.1.1
Core Features
16-BIT ARCHITECTURE
Central to all PIC24F devices is the 16-bit modified Harvard architecture, first introduced with Microchip's dsPIC(R) digital signal controllers. The PIC24F CPU core offers a wide range of enhancements, such as: * 16-bit data and 24-bit address paths with the ability to move information between data and memory spaces * Linear addressing of up to 12 Mbytes (program space) and 64 Kbytes (data) * A 16-element working register array with built-in software stack support * A 17 x 17 hardware multiplier with support for integer math * Hardware support for 32 by 16-bit division * An instruction set that supports multiple addressing modes and is optimized for high-level languages such as `C' * Operational performance up to 16 MIPS
1.1.4
EASY MIGRATION
1.1.2
POWER-SAVING TECHNOLOGY
All of the devices in the PIC24FJ256GB110 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: * On-the-Fly Clock Switching: The device clock can be changed under software control to the Timer1 source or the internal, low-power RC oscillator during operation, allowing the user to incorporate power-saving ideas into their software designs.
Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in migrating from one device to the next larger, or even in jumping from 64-pin to 100-pin devices. The PIC24F family is pin-compatible with devices in the dsPIC33 family, and shares some compatibility with the pinout schema for PIC18 and dsPIC30. This extends the ability of applications to grow from the relatively simple, to the powerful and complex, yet still selecting a Microchip device.
(c) 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 9
PIC24FJ256GB110 FAMILY
1.2 USB On-The-Go
With the PIC24FJ256GB110 family of devices, Microchip introduces USB On-The-Go functionality on a single chip to its product line. This new module provides on-chip functionality as a target device compatible with the USB 2.0 standard, as well as limited stand-alone functionality as a USB embedded host. By implementing USB Host Negotiation Protocol (HNP), the module can also dynamically switch between device and host operation, allowing for a much wider range of versatile USB-enabled applications on a microcontroller platform. In addition to USB host functionality, PIC24FJ256GB110 family devices provide a true single-chip USB solution, including an on-chip transceiver and voltage regulator, and a voltage boost generator for sourcing bus power during host operations. * Parallel Master/Enhanced Parallel Slave Port: One of the general purpose I/O ports can be reconfigured for enhanced parallel data communications. In this mode, the port can be configured for both master and slave operations, and supports 8-bit and 16-bit data transfers with up to 16 external address lines in Master modes. * Real-Time Clock/Calendar: This module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application.
1.4
Details on Individual Family Members
Devices in the PIC24FJ256GB110 family are available in 64-pin, 80-pin and 100-pin packages. The general block diagram for all devices is shown in Figure 1-1. The devices are differentiated from each other in four ways: 1. Flash program memory (64 Kbytes for PIC24FJ64GB1 devices, 128 Kbytes for PIC24FJ128GB1 devices, 192 Kbytes for PIC24FJ192GB1 devices and 256 Kbytes for PIC24FJ256GB1 devices). Available I/O pins and ports (51 pins on 6 ports for 64-pin devices, 65 pins on 7 ports for 80-pin devices and 83 pins on 7 ports for 100-pin devices). Available Interrupt-on-Change Notification (ICN) inputs (49 on 64-pin devices, 63 on 80-pin devices, and 81 on 100-pin devices). Available remappable pins (29 pins on 64-pin devices, 40 pins on 80-pin devices and 44 pins on 100-pin devices)
1.3
Other Special Features
* Peripheral Pin Select: The peripheral pin select feature allows most digital peripherals to be mapped over a fixed set of digital I/O pins. Users may independently map the input and/or output of any one of the many digital peripherals to any one of the I/O pins. * Communications: The PIC24FJ256GB110 family incorporates a range of serial communication peripherals to handle a range of application requirements. There are three independent I2C modules that support both Master and Slave modes of operation. Devices also have, through the peripheral pin select feature, four independent UARTs with built-in IrDA encoder/decoders and three SPI modules. * Analog Features: All members of the PIC24FJ256GB110 family include a 10-bit A/D Converter module and a triple comparator module. The A/D module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, as well as faster sampling speeds. The comparator module includes three analog comparators that are configurable for a wide range of operations. * CTMU Interface: In addition to their other analog features, members of the PIC24FJ256GB110 family include the brand new CTMU interface module. This provides a convenient method for precision time measurement and pulse generation, and can serve as an interface for capacitive sensors.
2.
3.
4.
All other features for devices in this family are identical. These are summarized in Table 1-1. A list of the pin features available on the PIC24FJ256GB110 family devices, sorted by function, is shown in Table 1-4. Note that this table shows the pin location of individual peripheral features and not how they are multiplexed on the same pin. This information is provided in the pinout diagrams in the beginning of the data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first.
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PIC24FJ256GB110 FAMILY
TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ256GB110 FAMILY: 64-PIN DEVICES
Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) I/O Ports Total I/O Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels Output Compare/PWM Channels Input Change Notification Interrupt Serial Communications: UART SPI (3-wire/4-wire) I2CTM Parallel Communications (PMP/PSP) JTAG Boundary Scan/Programming 10-Bit Analog-to-Digital Module (input channels) Analog Comparators CTMU Interface Resets (and delays) 4(1) 3(1) 3 Yes Yes 16 3 Yes POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations 64-Pin TQFP Peripherals are accessible through remappable pins. 5(1) 2 9(1) 9(1) 49 64K 22,016 64GB106 128GB106 128K 44,032 16,384 66 (62/4) Ports B, C, D, E, F, G 51 29 (28 I/O, 1 Input only) 192GB106 192K 67,072 256GB106 256K 87,552 DC - 32 MHz
Instruction Set Packages Note 1:
(c) 2008 Microchip Technology Inc.
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PIC24FJ256GB110 FAMILY
TABLE 1-2: DEVICE FEATURES FOR THE PIC24FJ256GB110 FAMILY: 80-PIN DEVICES
Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) I/O Ports Total I/O Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels Output Compare/PWM Channels Input Change Notification Interrupt Serial Communications: UART SPI (3-wire/4-wire) I2CTM Parallel Communications (PMP/PSP) JTAG Boundary Scan/Programming 10-Bit Analog-to-Digital Module (input channels) Analog Comparators CTMU Interface Resets (and delays) 4(1) 3(1) 3 Yes Yes 16 3 Yes POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations 80-Pin TQFP Peripherals are accessible through remappable pins. 5(1) 2 9(1) 9(1) 63 64K 22,016 64GB108 128GB108 128K 44,032 16,384 66 (62/4) Ports A, B, C, D, E, F, G 65 40 (31 I/O, 9 Input only) 192GB108 192K 67,072 256GB108 256K 87,552 DC - 32 MHz
Instruction Set Packages Note 1:
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TABLE 1-3: DEVICE FEATURES FOR THE PIC24FJ256GB110 FAMILY: 100-PIN DEVICES
Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) I/O Ports Total I/O Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels Output Compare/PWM Channels Input Change Notification Interrupt Serial Communications: UART SPI (3-wire/4-wire) I2CTM Parallel Communications (PMP/PSP) JTAG Boundary Scan/Programming 10-Bit Analog-to-Digital Module (input channels) Analog Comparators CTMU Interface Resets (and delays) 4(1) 3(1) 3 Yes Yes 16 3 Yes POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations 100-Pin TQFP Peripherals are accessible through remappable pins. 5(1) 2 9(1) 9(1) 81 64K 22,016 64GB110 128GB110 128K 44,032 16,384 66 (62/4) Ports A, B, C, D, E, F, G 83 44 (32 I/O, 12 Input only) 192GB110 192K 67,072 256GB110 256K 87,552 DC - 32 MHz
Instruction Set Packages Note 1:
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PIC24FJ256GB110 FAMILY
FIGURE 1-1: PIC24FJ256GB110 FAMILY GENERAL BLOCK DIAGRAM
Data Bus
16 8 PSV & Table Data Access Control Block 16 16 Data Latch 23 PCH PCL Program Counter Repeat Stack Control Control Logic Logic Data RAM Address Latch 16 16 Read AGU Write AGU PORTB (16 I/O) PORTA(1) (13 I/O)
Interrupt Controller
23 Address Latch Program Memory Data Latch
PORTC(1) (8 I/O)
Address Bus
24 Inst Latch Inst Register Instruction Decode & Control OSCO/CLKO OSCI/CLKI Timing Generation FRC/LPRC Oscillators Precision Band Gap Reference ENVREG Voltage Regulator Control Signals Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer BOR and LVD(2) Literal Data
EA MUX 16 16
16
PORTD(1) (16 I/O)
PORTE(1) Divide Support 17x17 Multiplier 16 x 16 W Reg Array (10 I/O)
REFO
16-Bit ALU 16
PORTF(1) (9 I/O)
PORTG(1) (12 I/O)
VDDCORE/VCAP
VDD, VSS
MCLR
Timer1
Timer2/3(3)
Timer4/5(3)
RTCC
10-Bit ADC
Comparators(3)
USB OTG
PMP/PSP PWM/OC 1-9(3) SPI 1/2/3(3)
IC 1-9(3) Note 1: 2: 3:
ICNs(1)
I2C 1/2/3
UART 1/2/3/4(3)
CTMU
Not all I/O pins or features are implemented on all device pinout configurations. See Table 1-4 for specific implementations by pin count. BOR functionality is provided when the on-board voltage regulator is enabled. These peripheral I/Os are only accessible through remappable pins.
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TABLE 1-4:
Function
PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS
Pin Number 64-Pin TQFP 16 15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 19 20 11 12 5 4 13 14 8 6 55 54 48 47 39 40 80-Pin TQFP 20 19 18 17 16 15 21 22 27 28 29 30 33 34 35 36 25 26 15 16 7 6 17 18 10 8 69 68 60 59 49 50 100-Pin TQFP 25 24 23 22 21 20 26 27 32 33 34 35 41 42 43 44 30 31 20 21 11 10 22 23 14 12 84 83 74 73 63 64 I/O Input Buffer ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA -- -- ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA -- Positive Supply for Analog modules. Ground Reference for Analog modules. Comparator 1 Input A. Comparator 1 Input B. Comparator 1 Input C. Comparator 1 Input D. Comparator 2 Input A. Comparator 2 Input B. Comparator 2 Input C. Comparator 2 Input D. Comparator 3 Input A. Comparator 3 Input B. Comparator 3 Input C. Comparator 3 Input D. Main Clock Input Connection. System Clock Output. A/D Analog Inputs. Description
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AVDD AVSS C1INA C1INB C1INC C1IND C2INA C2INB C2INC C2IND C3INA C3INB C3INC C3IND CLKI CLKO Legend:
I I I I I I I I I I I I I I I I P P I I I I I I I I I I I I I O
TTL = TTL input buffer ANA = Analog level input/output
ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer
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PIC24FJ256GB110 FAMILY
TABLE 1-4:
Function
PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number 64-Pin TQFP 48 47 16 15 14 13 12 11 4 5 6 8 30 52 53 54 55 31 32 -- -- -- 40 39 17 18 21 22 23 24 27 28 29 -- -- -- -- -- -- -- -- -- -- 80-Pin TQFP 60 59 20 19 18 17 16 15 6 7 8 10 36 66 67 68 69 39 40 65 37 38 50 49 21 22 27 28 29 30 33 34 35 -- -- -- -- -- -- -- -- 23 24 100-Pin TQFP 74 73 25 24 23 22 21 20 10 11 12 14 44 81 82 83 84 49 50 80 47 48 64 63 26 27 32 33 34 35 41 42 43 17 38 58 59 60 61 91 92 28 29 I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Description
CN0 CN1 CN2 CN3 CN4 CN5 CN6 CN7 CN8 CN9 CN10 CN11 CN12 CN13 CN14 CN15 CN16 CN17 CN18 CN19 CN20 CN21 CN22 CN23 CN24 CN25 CN26 CN27 CN28 CN29 CN30 CN31 CN32 CN33 CN34 CN35 CN36 CN37 CN38 CN39 CN40 CN41 CN42 Legend:
I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I
Interrupt-on-Change Inputs.
TTL = TTL input buffer ANA = Analog level input/output
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TABLE 1-4:
Function
PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number 64-Pin TQFP -- -- -- -- -- -- 46 49 50 51 42 43 44 45 -- 60 61 62 63 64 1 2 3 -- -- 58 59 -- 33 -- -- -- -- -- -- -- -- -- 28 27 29 23 80-Pin TQFP 52 53 4 -- 5 -- 58 61 62 63 54 55 56 57 64 76 77 78 79 80 1 2 3 13 14 72 73 42 41 43 -- -- 75 74 -- -- -- -- 34 33 35 29 100-Pin TQFP 66 67 6 7 8 9 72 76 77 78 68 69 70 71 79 93 94 98 99 100 3 4 5 18 19 87 88 52 51 53 40 39 90 89 96 97 95 1 42 41 43 34 I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ANA ANA -- -- CTMU External Edge Input 1. CTMU External Edge Input 2. CTMU Pulse Output. Comparator Voltage Reference Output. Description
CN43 CN44 CN45 CN46 CN47 CN48 CN49 CN50 CN51 CN52 CN53 CN54 CN55 CN56 CN57 CN58 CN59 CN60 CN61 CN62 CN63 CN64 CN65 CN66 CN67 CN68 CN69 CN70 CN71 CN74 CN75 CN76 CN77 CN78 CN79 CN80 CN81 CN82 CTED1 CTED2 CTPLS CVREF Legend:
I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I O O
Interrupt-on-Change Inputs.
TTL = TTL input buffer ANA = Analog level input/output
ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer
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Preliminary
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PIC24FJ256GB110 FAMILY
TABLE 1-4:
Function
PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number 64-Pin TQFP 37 36 46 42 50 43 57 46 7 39 40 15 16 17 18 11 12 30 29 8 6 5 4 16 22 32 31 28 27 24 23 45 44 51 80-Pin TQFP 47 46 58 54 62 55 71 58 9 49 50 19 20 21 22 15 16 36 35 10 8 7 6 24 23 40 39 34 33 30 29 57 56 63 100-Pin TQFP 57 56 72 68 77 69 86 72 13 63 64 24 25 26 27 20 21 44 43 14 12 11 10 29 28 50 49 42 41 35 34 71 70 78 I/O Input Buffer -- -- -- -- -- -- ST ST ST ANA ANA ST ST ST ST ST ST ST ST -- -- -- -- -- -- -- -- -- -- -- -- ST/TTL ST -- Parallel Master Port Chip Select 1 Strobe/Address Bit 15. Parallel Master Port Chip Select 2 Strobe/Address Bit 14. Parallel Master Port Byte Enable Strobe. Description
D+ DDMH DMLN DPH DPLN ENVREG INT0 MCLR OSCI OSCO PGEC1 PGED1 PGEC2 PGED2 PGEC3 PGED3 PMA0 PMA1 PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMA11 PMA12 PMA13 PMCS1 PMCS2 PMBE Legend:
I/O I/O O O O O I I I I O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O I/O O O
USB Differential Plus line (internal transceiver). USB Differential Minus line (internal transceiver). D- External Pull-up Control Output. D- External Pull-down Control Output. D+ External Pull-up Control Output. D+ External Pull-down Control Output. Voltage Regulator Enable. External Interrupt Input. Master Clear (device Reset) Input. This line is brought low to cause a Reset. Main Oscillator Input Connection. Main Oscillator Output Connection. In-Circuit Debugger/Emulator/ICSPTM Programming Clock. In-Circuit Debugger/Emulator/ICSP Programming Data. In-Circuit Debugger/Emulator/ICSP Programming Clock. In-Circuit Debugger/Emulator/ICSP Programming Data. In-Circuit Debugger/Emulator/ICSP Programming Clock. In-Circuit Debugger/Emulator/ICSP Programming Data. Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address (Demultiplexed Master modes).
TTL = TTL input buffer ANA = Analog level input/output
ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer
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TABLE 1-4:
Function
PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number 64-Pin TQFP 60 61 62 63 64 1 2 3 53 52 -- -- -- -- -- -- -- -- -- -- -- -- 16 15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 80-Pin TQFP 76 77 78 79 80 1 2 3 67 66 -- -- -- -- -- -- -- -- 23 24 52 53 20 19 18 17 16 15 21 22 27 28 29 30 33 34 35 36 100-Pin TQFP 93 94 98 99 100 3 4 5 82 81 17 38 58 59 60 61 91 92 28 29 66 67 25 24 23 22 21 20 26 27 32 33 34 35 41 42 43 44 I/O Input Buffer ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL -- -- ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer PORTB Digital I/O. Parallel Master Port Read Strobe. Parallel Master Port Write Strobe. PORTA Digital I/O. Description
PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMRD PMWR RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA9 RA10 RA14 RA15 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RB8 RB9 RB10 RB11 RB12 RB13 RB14 RB15 Legend:
I/O I/O I/O I/O I/O I/O I/O I/O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Parallel Master Port Data (Demultiplexed Master mode) or Address/Data (Multiplexed Master modes).
TTL = TTL input buffer ANA = Analog level input/output
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Preliminary
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PIC24FJ256GB110 FAMILY
TABLE 1-4:
Function
PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number 64-Pin TQFP -- -- -- -- 39 47 48 40 18 46 49 50 51 52 53 54 55 42 43 44 45 -- -- -- -- 60 61 62 63 64 1 2 3 -- -- 30 80-Pin TQFP 4 -- 5 -- 49 59 60 50 22 58 61 62 63 66 67 68 69 54 55 56 57 64 65 37 38 76 77 78 79 80 1 2 3 13 14 36 100-Pin TQFP 6 7 8 9 63 73 74 64 27 72 76 77 78 81 82 83 84 68 69 70 71 79 80 47 48 93 94 98 99 100 3 4 5 18 19 44 I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST -- Reference Clock Output. ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer PORTE Digital I/O. USB Receive Input (from external transceiver). PORTD Digital I/O. PORTC Digital I/O. Description
RC1 RC2 RC3 RC4 RC12 RC13 RC14 RC15 RCV RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RD8 RD9 RD10 RD11 RD12 RD13 RD14 RD15 RE0 RE1 RE2 RE3 RE4 RE5 RE6 RE7 RE8 RE9 REFO Legend:
I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O
TTL = TTL input buffer ANA = Analog level input/output
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TABLE 1-4:
Function
PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number 64-Pin TQFP 58 59 -- 33 31 32 -- -- -- -- -- 37 36 4 5 6 8 -- -- -- -- 16 15 42 44 43 -- 17 18 21 22 31 46 45 14 29 -- 33 32 11 6 80-Pin TQFP 72 73 42 41 39 40 43 -- -- 75 74 47 46 6 7 8 10 -- -- -- -- 20 19 54 56 55 38 21 22 27 28 39 58 57 18 35 43 41 40 15 8 100-Pin TQFP 87 88 52 51 49 50 53 40 39 90 89 57 56 10 11 12 14 96 97 95 1 25 24 68 70 69 48 26 27 32 33 49 72 71 23 43 53 51 50 20 12 I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Remappable Peripheral (input or output). PORTG Digital I/O. PORTF Digital I/O. Description
RF0 RF1 RF2 RF3 RF4 RF5 RF8 RF12 RF13 RG0 RG1 RG2 RG3 RG6 RG7 RG8 RG9 RG12 RG13 RG14 RG15 RP0 RP1 RP2 RP3 RP4 RP5 RP6 RP7 RP8 RP9 RP10 RP11 RP12 RP13 RP14 RP15 RP16 RP17 RP18 RP19 Legend:
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
TTL = TTL input buffer ANA = Analog level input/output
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PIC24FJ256GB110 FAMILY
TABLE 1-4:
Function
PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number 64-Pin TQFP 53 4 51 50 49 52 5 8 12 30 -- -- -- -- -- -- -- 48 -- -- -- -- -- -- 42 44 32 2 43 31 3 47 48 48 27 28 24 23 33 12 80-Pin TQFP 67 6 63 62 61 66 7 10 16 36 42 -- -- 13 14 53 52 60 4 -- 5 -- 64 37 54 56 52 2 55 53 3 59 60 60 33 34 14 13 41 16 100-Pin TQFP 82 10 78 77 76 81 11 14 21 44 52 39 40 18 19 67 66 74 6 7 8 9 79 47 68 66 58 4 67 59 5 73 74 74 38 60 61 17 51 21 I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST -- I2C I2C I2C I2C I2C I2C ANA ANA ST ST ST -- ST ST -- Real-Time Clock Alarm/Seconds Pulse Output. I2C1 Synchronous Serial Clock Input/Output. I2C2 Synchronous Serial Clock Input/Output. I2C3 Synchronous Serial Clock Input/Output. I2C1 Data Input/Output. I2C2 Data Input/Output. I2C3 Data Input/Output. Secondary Oscillator/Timer1 Clock Input. Secondary Oscillator/Timer1 Clock Output. Timer1 Clock. JTAG Test Clock/Programming Clock Input. JTAG Test Data/Programming Data Input. JTAG Test Data Output. JTAG Test Mode Select Input. USB OTG ID (OTG mode only). USB Output Enable Control (for external transceiver). Remappable Peripheral (input only). Description
RP20 RP21 RP22 RP23 RP24 RP25 RP26 RP27 RP28 RP29 RP30 RP31 RPI32 RPI33 RPI34 RPI35 RPI36 RPI37 RPI38 RPI39 RPI40 RPI41 RPI42 RPI43 RTCC SCL1 SCL2 SCL3 SDA1 SDA2 SDA3 SOSCI SOSCO T1CK TCK TDI TDO TMS USBID USBOEN Legend:
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I I I I O I/O I/O I/O I/O I/O I/O I O I I I O I I O
Remappable Peripheral (input or output).
TTL = TTL input buffer ANA = Analog level input/output
ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer
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TABLE 1-4:
Function
PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number 64-Pin TQFP 34 11 58 56 58 59 49 80-Pin TQFP 44 15 72 70 72 73 61 12, 32, 48 70 18 17 23 24 11, 31, 51 45 100-Pin TQFP 54 20 87 85 87 88 76 2, 16, 37, 46, 62 85 23 22 28 29 15, 36, 45, 65, 75 55 I/O Input Buffer -- -- ANA -- ST ST -- -- -- ST ST ANA ANA -- -- Description
VBUS VBUSON VBUSST VCAP VCMPST1 VCMPST2 VCPCON VDD VDDCORE VMIO VPIO VREFVREF+ VSS VUSB Legend:
P O I P I I O P P I/O I/O I I P P
USB Voltage, Host mode (5V). USB OTG External Charge Pump Control. USB OTG Internal Charge Pump Feedback Control. External Filter Capacitor Connection (regulator enabled). USB VBUS Boost Generator, Comparator Input 1. USB VBUS Boost Generator, Comparator Input 2. USB OTG VBUS PWM/Charge Output. Positive Supply for Peripheral Digital Logic and I/O Pins. Positive Supply for Microcontroller Core Logic (regulator disabled). USB Differential Minus Input/Output (external transceiver). USB Differential Plus Input/Output (external transceiver). A/D and Comparator Reference Voltage (low) Input. A/D and Comparator Reference Voltage (high) Input. Ground Reference for Logic and I/O Pins. USB Voltage (3.3V)
10, 26, 38 56 14 13 15 16 9, 25, 41 35
TTL = TTL input buffer ANA = Analog level input/output
ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer
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PIC24FJ256GB110 FAMILY
NOTES:
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2.0
Note:
CPU
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 2. CPU" (DS39703).
For most instructions, the core is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing trinary operations (that is, A + B = C) to be executed in a single cycle. A high-speed, 17-bit by 17-bit multiplier has been included to significantly enhance the core arithmetic capability and throughput. The multiplier supports Signed, Unsigned and Mixed mode, 16-bit by 16-bit or 8-bit by 8-bit, integer multiplication. All multiply instructions execute in a single cycle. The 16-bit ALU has been enhanced with integer divide assist hardware that supports an iterative non-restoring divide algorithm. It operates in conjunction with the REPEAT instruction looping mechanism and a selection of iterative divide instructions to support 32-bit (or 16-bit), divided by 16-bit, integer signed and unsigned division. All divide operations require 19 cycles to complete but are interruptible at any cycle boundary. The PIC24F has a vectored exception scheme with up to 8 sources of non-maskable traps and up to 118 interrupt sources. Each interrupt source can be assigned to one of seven priority levels. A block diagram of the CPU is shown in Figure 2-1.
The PIC24F CPU has a 16-bit (data) modified Harvard architecture with an enhanced instruction set and a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M instructions of user program memory space. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction and the table instructions. Overhead-free program loop constructs are supported using the REPEAT instructions, which are interruptible at any point. PIC24F devices have sixteen, 16-bit working registers in the programmer's model. Each of the working registers can act as a data, address or address offset register. The 16th working register (W15) operates as a Software Stack Pointer for interrupts and calls. The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K word boundary defined by the 8-bit Program Space Visibility Page Address (PSVPAG) register. The program to data space mapping feature lets any instruction access program space as if it were data space. The Instruction Set Architecture (ISA) has been significantly enhanced beyond that of the PIC18, but maintains an acceptable level of backward compatibility. All PIC18 instructions and addressing modes are supported, either directly, or through simple macros. Many of the ISA enhancements have been driven by compiler efficiency needs. The core supports Inherent (no operand), Relative, Literal, Memory Direct and three groups of addressing modes. All modes support Register Direct and various Register Indirect modes. Each group offers up to seven addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements.
2.1
Programmer's Model
The programmer's model for the PIC24F is shown in Figure 2-2. All registers in the programmer's model are memory mapped and can be manipulated directly by instructions. A description of each register is provided in Table 2-1. All registers associated with the programmer's model are memory mapped.
(c) 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 25
PIC24FJ256GB110 FAMILY
FIGURE 2-1:
PSV & Table Data Access Control Block Interrupt Controller 8 23 23 PCH PCL Program Counter Loop Stack Control Control Logic Logic Data RAM Address Latch 16 RAGU WAGU 16 Data Bus 16 16 Data Latch 16
PIC24F CPU CORE BLOCK DIAGRAM
23
Address Latch
Program Memory Address Bus Data Latch 24 ROM Latch 16 Literal Data 16 EA MUX
Instruction Decode & Control
Instruction Reg
Control Signals to Various Blocks
Hardware Multiplier Divide Support
16 x 16 W Register Array 16
16-Bit ALU 16
To Peripheral Modules
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Preliminary
(c) 2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
TABLE 2-1:
W0 through W15 PC SR SPLIM TBLPAG PSVPAG RCOUNT CORCON
CPU CORE REGISTERS
Description Working Register Array 23-Bit Program Counter ALU STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Register CPU Control Register
Register(s) Name
FIGURE 2-2:
PROGRAMMER'S MODEL
15 0 W0 (WREG) W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 Frame Pointer Stack Pointer 0 Stack Pointer Limit Value Register Program Counter Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Register Working/Address Registers
Divider Working Registers
Multiplier Registers
SPLIM 22 PC 7 TBLPAG 7 PSVPAG 15 RCOUNT 15 SRH SRL
0 0 0 0
0
0
0 ALU STATUS Register (SR)
-- -- -- -- -- -- -- DC
IPL 2 1 0 RA N OV Z C
15
0 CPU Control Register (CORCON)
-- -- -- -- -- -- -- -- -- -- -- -- IPL3 PSV -- --
Registers or bits shadowed for PUSH.S and POP.S instructions.
(c) 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 27
PIC24FJ256GB110 FAMILY
2.2 CPU Control Registers
SR: ALU STATUS REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 DC bit 8 R/W-0(1) IPL1
(2)
REGISTER 2-1:
U-0 -- bit 15 R/W-0(1) IPL2 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-9 bit 8
(2)
R/W-0(1) IPL0
(2)
R-0 RA
R/W-0 N
R/W-0 OV
R/W-0 Z
R/W-0 C bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' DC: ALU Half Carry/Borrow bit 1 = A carry out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry out from the 4th or 8th low-order bit of the result has occurred IPL2:IPL0: CPU Interrupt Priority Level Status bits(1,2) 111 = CPU interrupt priority level is 7 (15); user interrupts disabled 110 = CPU interrupt priority level is 6 (14) 101 = CPU interrupt priority Level is 5 (13) 100 = CPU interrupt priority level is 4 (12) 011 = CPU interrupt priority level is 3 (11) 010 = CPU interrupt priority level is 2 (10) 001 = CPU interrupt priority level is 1 (9) 000 = CPU interrupt priority level is 0 (8) RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress N: ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) OV: ALU Overflow bit 1 = Overflow occurred for signed (2's complement) arithmetic in this arithmetic operation 0 = No overflow has occurred Z: ALU Zero bit 1 = An operation which effects the Z bit has set it at some time in the past 0 = The most recent operation which effects the Z bit has cleared it (i.e., a non-zero result) C: ALU Carry/Borrow bit 1 = A carry out from the Most Significant bit of the result occurred 0 = No carry out from the Most Significant bit of the result occurred The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1. The IPL Status bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1: 2:
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(c) 2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
REGISTER 2-2:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-4 bit 3 C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- R/C-0 IPL3
(1)
CORCON: CPU CONTROL REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 PSV U-0 -- U-0 -- bit 0
Unimplemented: Read as `0' IPL3: CPU Interrupt Priority Level Status bit(1) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space Unimplemented: Read as `0' User interrupts are disabled when IPL3 = 1.
bit 2
bit 1-0 Note 1:
2.3
Arithmetic Logic Unit (ALU)
The PIC24F ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2's complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location.
The PIC24F CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit divisor division.
2.3.1
MULTIPLIER
The ALU contains a high-speed, 17-bit x 17-bit multiplier. It supports unsigned, signed or mixed sign operation in several multiplication modes: 1. 2. 3. 4. 5. 6. 7. 16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit unsigned x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned
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PIC24FJ256GB110 FAMILY
2.3.2 DIVIDER 2.3.3 MULTI-BIT SHIFT SUPPORT
The divide block supports signed and unsigned integer divide operations with the following data sizes: 1. 2. 3. 4. 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The PIC24F ALU supports both single bit and single-cycle, multi-bit arithmetic and logic shifts. Multi-bit shifts are implemented using a shifter block, capable of performing up to a 15-bit arithmetic right shift, or up to a 15-bit left shift, in a single cycle. All multi-bit shift instructions only support Register Direct Addressing for both the operand source and result destination. A full summary of instructions that use the shift operation is provided below in Table 2-2.
The quotient for all divide instructions ends up in W0 and the remainder in W1. Sixteen-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn), and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute.
TABLE 2-2:
Instruction ASR SL LSR
INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION
Description Arithmetic shift right source register by one or more bits. Shift left source register by one or more bits. Logical shift right source register by one or more bits.
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(c) 2008 Microchip Technology Inc.
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3.0 MEMORY ORGANIZATION
As Harvard architecture devices, PIC24F microcontrollers feature separate program and data memory spaces and busses. This architecture also allows the direct access of program memory from the data space during code execution. from either the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping, as described in Section 3.3 "Interfacing Program and Data Memory Spaces". User access to the program memory space is restricted to the lower half of the address range (000000h to 7FFFFFh). The exception is the use of TBLRD/TBLWT operations which use TBLPAG<7> to permit access to the Configuration bits and Device ID sections of the configuration memory space. Memory maps for the PIC24FJ256GB110 family of devices are shown in Figure 3-1.
3.1
Program Address Space
The program address memory space of the PIC24FJ256GB110 family devices is 4M instructions. The space is addressable by a 24-bit value derived
FIGURE 3-1:
PROGRAM SPACE MEMORY MAP FOR PIC24FJ256GB110 FAMILY DEVICES
PIC24FJ128GB1XX
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Flash Program Memory (44K instructions)
PIC24FJ64GB1XX
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Flash Program Memory (22K instructions) Flash Config Words User Memory Space
PIC24FJ192GB1XX
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table
PIC24FJ256GB1XX
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table 000000h 000002h 000004h 0000FEh 000100h 000104h 0001FEh 000200h
User Flash Program Memory (67K instructions)
Flash Config Words
User Flash Program Memory (87K instructions)
00ABFEh 00AC00h 0157FEh 015800h 020BFEh 020C00h
Flash Config Words Unimplemented Read `0' Unimplemented Read `0'
Flash Config Words Unimplemented Read `0'
02ABFEh 02AC00h
Unimplemented Read `0'
7FFFFFh 800000h
Reserved Configuration Memory Space
Reserved
Reserved
Reserved
Device Config Registers
Device Config Registers
Device Config Registers
Device Config Registers
F7FFFEh F80000h F8000Eh F80010h
Reserved
Reserved
Reserved
Reserved
DEVID (2)
DEVID (2)
DEVID (2)
DEVID (2)
FEFFFEh FF0000h FFFFFFh
Note:
Memory areas are not shown to scale.
(c) 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 31
PIC24FJ256GB110 FAMILY
3.1.1 PROGRAM MEMORY ORGANIZATION 3.1.3 FLASH CONFIGURATION WORDS
The program memory space is organized in word-addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (Figure 3-2). Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. This arrangement also provides compatibility with data memory space addressing and makes it possible to access data in the program memory space. In PIC24FJ256GB110 family devices, the top three words of on-chip program memory are reserved for configuration information. On device Reset, the configuration information is copied into the appropriate Configuration registers. The addresses of the Flash Configuration Word for devices in the PIC24FJ256GB110 family are shown in Table 3-1. Their location in the memory map is shown with the other memory vectors in Figure 3-1. The Configuration Words in program memory are a compact format. The actual Configuration bits are mapped in several different registers in the configuration memory space. Their order in the Flash Configuration Words do not reflect a corresponding arrangement in the configuration space. Additional details on the device Configuration Words are provided in Section 25.1 "Configuration Bits".
3.1.2
HARD MEMORY VECTORS
All PIC24F devices reserve the addresses between 00000h and 000200h for hard coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user at 000000h with the actual address for the start of code at 000002h. PIC24F devices also have two interrupt vector tables, located from 000004h to 0000FFh and 000100h to 0001FFh. These vector tables allow each of the many device interrupt sources to be handled by separate ISRs. A more detailed discussion of the interrupt vector tables is provided in Section 6.1 "Interrupt Vector Table".
TABLE 3-1:
FLASH CONFIGURATION WORDS FOR PIC24FJ256GB110 FAMILY DEVICES
Program Memory (Words) 22,016 44,032 67,072 87,552 Configuration Word Addresses 00ABFAh: 00ABFEh 0157FAh: 0157FEh 020BFAh: 020BFEh 02ABFAh: 02ABFEh
Device
PIC24FJ64GB PIC24FJ128GB PIC24FJ192GB PIC24FJ256GB
FIGURE 3-2:
MSW Address 000001h 000003h 000005h 000007h
PROGRAM MEMORY ORGANIZATION
most significant word 23 00000000 00000000 00000000 00000000 Program Memory `Phantom' Byte (read as `0') Instruction Width 16 least significant word 8 0 000000h 000002h 000004h 000006h PC Address (LSW Address)
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3.2 Data Address Space
The PIC24F core has a separate, 16-bit wide data memory space, addressable as a single linear range. The data space is accessed using two Address Generation Units (AGUs), one each for read and write operations. The data space memory map is shown in Figure 3-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This gives a data space address range of 64 Kbytes or 32K words. The lower half of the data memory space (that is, when EA<15> = 0) is used for implemented memory addresses, while the upper half (EA<15> = 1) is reserved for the program space visibility area (see Section 3.3.3 "Reading Data from Program Memory Using Program Space Visibility"). PIC24FJ256GB110 family devices implement a total of 16 Kbytes of data memory. Should an EA point to a location outside of this area, an all zero word or byte will be returned.
3.2.1
DATA SPACE WIDTH
The data memory space is organized in byte-addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes of each word have even addresses, while the Most Significant Bytes have odd addresses.
FIGURE 3-3:
DATA SPACE MEMORY MAP FOR PIC24FJ256GB110 FAMILY DEVICES
MSB Address 0001h 07FFh 0801h 1FFFh 2001h Data RAM LSB Address 0000h 07FEh 0800h 1FFEh 2000h SFR Space
MSB SFR Space
LSB
Near Data Space
Implemented Data RAM
47FFh 4801h Unimplemented Read as `0' 7FFFh 8001h
47FEh 4800h
7FFFh 8000h
Program Space Visibility Area
FFFFh
FFFEh
Note:
Data memory areas are not shown to scale.
(c) 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 33
PIC24FJ256GB110 FAMILY
3.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT
To maintain backward compatibility with PIC(R) devices and improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations. As a consequence of byte accessibility, all Effective Address calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result in a value of Ws + 1 for byte operations and Ws + 2 for word operations. Data byte reads will read the complete word which contains the byte, using the LSb of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel, byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register which matches the byte address. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap will be generated. If the error occurred on a read, the instruction underway is completed; if it occurred on a write, the instruction will be executed but the write will not occur. In either case, a trap is then executed, allowing the system and/or user to examine the machine state prior to execution of the address Fault. All byte loads into any W register are loaded into the Least Significant Byte. The Most Significant Byte is not modified. A sign-extend instruction (SE) is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address. Although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions operate only on words.
3.2.3
NEAR DATA SPACE
The 8-Kbyte area between 0000h and 1FFFh is referred to as the near data space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. The remainder of the data space is addressable indirectly. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing with a 16-bit address field.
3.2.4
SFR SPACE
The first 2 Kbytes of the near data space, from 0000h to 07FFh, are primarily occupied with Special Function Registers (SFRs). These are used by the PIC24F core and peripheral modules for controlling the operation of the device. SFRs are distributed among the modules that they control and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as `0'. A diagram of the SFR space, showing where SFRs are actually implemented, is shown in Table 3-2. Each implemented area indicates a 32-byte region where at least one address is implemented as an SFR. A complete listing of implemented SFRs, including their addresses, is shown in Tables 3-3 through 3-30.
TABLE 3-2:
IMPLEMENTED REGIONS OF SFR DATA SPACE
SFR Space Address xx00 xx20 Core Timers I2CTM A/D -- -- PMP -- UART A/D/CTMU -- -- RTC/Comp -- SPI/UART -- -- -- CRC System xx40 xx60 ICN Capture SPI/I2C -- -- -- -- NVM/PMD -- -- SPI -- UART -- USB -- PPS -- -- -- -- xx80 xxA0 Interrupts Compare I/O -- -- -- -- -- xxC0 xxE0 --
000h 100h 200h 300h 400h 500h 600h 700h
Legend: -- = No implemented SFRs in this block
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(c) 2008 Microchip Technology Inc.
TABLE 3-3:
Bit 13 Working Register 0 Working Register 1 Working Register 2 Working Register 3 Working Register 4 Working Register 5 Working Register 6 Working Register 7 Working Register 8 Working Register 9 Working Register 10 Working Register 11 Working Register 12 Working Register 13 Working Register 14 Working Register 15 Stack Pointer Limit Value Register Program Counter Low Word Register -- -- -- -- -- -- -- -- -- -- -- -- -- -- DC -- -- -- -- -- Repeat Loop Counter Register IPL2 -- IPL1 -- IPL0 -- Disable Interrupts Counter Register RA -- N IPL3 OV PSV Z -- C -- -- -- -- -- -- -- -- -- -- -- Program Counter Register High Byte Table Memory Page Address Register Program Space Visibility Page Address Register Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CPU CORE REGISTERS MAP
All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0800 xxxx 0000 0000 0000 0000 xxxx 0000 0000 xxxx
File Name
Addr
Bit 15
Bit 14
WREG0
0000
WREG1
0002
WREG2
0004
WREG3
0006
WREG4
0008
WREG5
000A
(c) 2008 Microchip Technology Inc.
WREG6
000C
WREG7
000E
WREG8
0010
WREG9
0012
WREG10
0014
WREG11
0016
WREG12
0018
WREG13
001A
WREG14
001C
WREG15
001E
SPLIM
0020
PCL
002E
PIC24FJ256GB110 FAMILY
Preliminary
PCH
0030
--
--
TBLPAG
0032
--
--
PSVPAG
0034
--
--
RCOUNT
0036
SR
0042
--
--
CORCON
0044
--
--
DISICNT
0052
--
--
Legend:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
DS39897B-page 35
TABLE 3-4:
Bit 13 CN13PDE CN29PDE CN61PDE -- -- CN9IE CN25IE CN41IE(1) CN57IE(1) CN56IE -- -- CN8PUE CN24PUE CN55PUE CN71PUE -- -- CN70PUE(1) -- CN69PUE CN54PUE CN53PUE CN23PUE CN22PUE CN7PUE CN6PUE CN5PUE CN4PUE -- -- -- -- CN71IE CN70IE(1) CN69IE CN68IE -- CN3PUE CN55IE CN54IE CN53IE CN52IE CN51IE CN67IE(1) -- -- CN9PUE CN25PUE CN40IE(2) CN39IE(2) CN38IE(2) CN37IE(2) CN36IE(2) CN35IE(2) CN24IE CN23IE CN22IE CN21IE(1) CN20IE(1) CN19IE(1) CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN18IE CN34IE(2) CN50IE CN66IE(1) CN82IE(2) CN2PUE CN18PUE CN51PUE -- -- CN50PUE CN68PUE CN67PUE(1) CN66PUE(1) -- -- -- -- -- -- -- CN71PDE CN70PDE(1) CN69PDE CN68PDE CN67PDE(1) CN66PDE(1) -- CN13IE CN29IE CN45IE(1) CN61IE CN77IE(1) -- CN13PUE CN29PUE CN61PUE -- -- -- -- -- -- -- -- CN60PUE CN59PUE CN58PUE CN57PUE(1) CN56PUE CN28PUE CN27PUE CN26PUE CN12PUE CN11PUE CN10PUE -- -- -- CN76IE(2) CN75IE(2) CN74IE(1) CN60IE CN59IE CN58IE CN44IE(1) CN43IE(1) CN42IE(1) CN28IE CN27IE CN26IE CN12IE CN11IE CN10IE -- -- -- CN60PDE CN59PDE CN58PDE CN57PDE(1) CN56PDE CN55PDE CN54PDE CN53PDE CN52PDE CN51PDE CN50PDE CN49PDE CN65PDE CN1IE CN17IE CN33IE(2) CN49IE CN65IE CN81IE(2) CN1PUE CN17PUE CN49PUE CN65PUE CN28PDE CN27PDE CN26PDE CN25PDE CN24PDE CN23PDE CN22PDE CN21PDE(1) CN20PDE(1) CN19PDE(1) CN18PDE CN17PDE CN12PDE CN11PDE CN10PDE CN9PDE CN8PDE CN7PDE CN6PDE CN5PDE CN4PDE CN3PDE CN2PDE CN1PDE CN0PDE CN16PDE CN32PDE CN64PDE CN0IE CN16IE CN32IE CN48IE(2) CN64IE CN80IE(2) CN0PUE CN16PUE CN32PUE CN52PUE CN64PUE Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 CN48PDE(2) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 CN48PUE(2) 0000 0000 CN82PUE(2) CN81PUE(2) CN80PUE(2) 0000
ICN REGISTER MAP
File Name
Addr
Bit 15
Bit 14
CNPD1
0054
CN15PDE
CN14PDE
DS39897B-page 36
CN82PDE(2) CN81PDE(2) CN80PDE(2) 0000 CN21PUE(1) CN20PUE(1) CN19PUE(1)
CNPD2
0056
CN31PDE
CN30PDE
CNPD3
0058 CN47PDE(1) CN46PDE(2) CN45PDE(1) CN44PDE(1) CN43PDE(1) CN42PDE(1) CN41PDE(1) CN40PDE(2) CN39PDE(2) CN38PDE(2) CN37PDE(2) CN36PDE(2) CN35PDE(2) CN34PDE(2) CN33PDE(2)
CNPD4
005A
CN63PDE
CN62PDE
CNPD5
005C CN79PDE(2) CN78PDE(1) CN77PDE(1) CN76PDE(2) CN75PDE(2) CN74PDE(1)
CNPD6
(2)
005E
--
--
CNEN1
0060
CN15IE
CN14IE
CNEN2
0062
CN31IE
CN30IE
CNEN3
0064
CN47IE(1)
CN46IE(2)
CNEN4
0066
CN63IE
CN62IE
CNEN5
0068
CN79IE(2)
CN78IE(1)
CNEN6(2) 006A
--
--
CNPU1
006C CN15PUE
CN14PUE
CNPU2
006E
CN31PUE
CN30PUE
CNPU3
0070 CN47PUE(1) CN46PUE(2) CN45PUE(1) CN44PUE(1) CN43PUE(1) CN42PUE(1) CN41PUE(1) CN40PUE(2) CN39PUE(2) CN38PUE(2) CN37PUE(2) CN36PUE(2) CN35PUE(2) CN34PUE(2) CN33PUE(2)
CNPU4
0072
CN63PUE
CN62PUE
CNPU5
0074 CN79PUE(2) CN78PUE(1) CN77PUE(1) CN76PUE(2) CN75PUE(2) CN74PUE(1)
PIC24FJ256GB110 FAMILY
Preliminary
CNPU6(2) 0076
--
--
Legend: Note 1: 2:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Unimplemented in 64-pin devices; read as `0'. Unimplemented in 64-pin and 80-pin devices; read as `0'.
(c) 2008 Microchip Technology Inc.
TABLE 3-5:
Bit 13 -- -- AD1IF INT2IF PMPIF -- CTMUIF IC9IF AD1IE INT2IE PMPIE -- CTMUIE IC9IE T1IP1 T2IP1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RTCIP2 RTCIP1 INT4IP2 INT4IP1 MI2C2P2 MI2C2P1 MI2C2P0 INT4IP0 RTCIP0 -- -- -- -- -- OC6IP2 OC6IP1 OC6IP0 IC4IP2 IC4IP1 IC4IP0 -- -- -- -- -- -- -- -- -- -- -- SPF3IP1 -- -- SPF3IP0 -- -- -- -- -- -- -- U2RXIP2 U2RXIP1 U2RXIP0 -- OC4IP2 OC4IP1 OC4IP0 -- IC7IP2 IC7IP1 IC7IP0 -- -- OC3IP2 INT2IP2 SPI2IP2 IC3IP2 OC5IP2 PMPIP2 SI2C2P2 INT3IP2 -- -- CMIP2 CMIP1 CMIP0 -- -- -- -- -- AD1IP2 SPI1IP2 SPI1IP1 SPI1IP0 -- SPF1IP2 SPF1IP1 AD1IP1 -- OC3IP1 INT2IP1 SPI2IP1 IC3IP1 OC5IP1 PMPIP1 SI2C2P1 INT3IP1 -- U1ERIP2 U1ERIP1 -- U3ERIP2 U3ERIP1 MI2C3P2 MI2C3P1 U4TXIP2 IC9IP2 U4TXIP1 IC9IP1 -- CNIP1 IC8IP1 T4IP1 U2TXIP1 -- IC5IP1 OC7IP1 -- -- -- -- CRCIP1 -- -- U3TXIP1 SPI3IP1 -- -- SPI3IP0 U3TXIP0 -- -- CRCIP0 -- -- -- -- OC7IP0 IC5IP0 -- U2TXIP0 T4IP0 IC8IP0 CNIP0 -- T2IP0 -- OC2IP2 OC2IP1 OC2IP0 -- IC2IP2 IC2IP1 T1IP0 -- OC1IP2 OC1IP1 OC1IP0 -- IC1IP2 IC1IP1 OC9IE SPI3IE SPF3IE U4TXIE U4RXIE U4ERIE USB1IE MI2C3IE SI2C3IE IC1IP0 IC2IP0 SPF1IP0 AD1IP0 MI2C1P0 -- OC3IP0 INT2IP0 SPI2IP0 IC3IP0 OC5IP0 PMPIP0 SI2C2P0 INT3IP0 -- U1ERIP0 -- CTMUIP2 CTMUIP1 CTMUIP0 U3ERIP0 MI2C3P0 U4TXIP0 IC9IP0 -- -- -- -- LVDIE -- -- -- -- -- -- -- -- -- -- INT4IE INT3IE -- OC8IE OC7IE OC6IE OC5IE IC6IE IC5IE IC4IE IC3IE -- -- -- CRCIE U3TXIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- T5IE T4IE OC4IE OC3IE -- IC8IE IC7IE -- INT1IE CNIE U1TXIE U1RXIE SPI1IE SPF1IE T3IE T2IE OC2IE IC2IE -- T1IE OC9IF SPI3IF SPF3IF U4TXIF U4RXIF U4ERIF USB1IF MI2C3IF SI2C3IF U3TXIF -- -- -- -- LVDIF -- -- -- -- CRCIF U2ERIF U3RXIF OC1IE CMIE -- MI2C2IE U2ERIE U3RXIE INT0IP2 -- T3IP2 U1TXIP2 SI2C1P2 INT1IP2 -- T5IP2 SPF2IP2 -- IC6IP2 OC8IP2 -- -- -- -- LVDIP2 -- -- SI2C3P2 OC9IP2 -- -- -- -- -- -- INT4IF INT3IF -- -- MI2C2IF OC8IF OC7IF OC6IF OC5IF IC6IF IC5IF IC4IF IC3IF -- -- -- T5IF T4IF OC4IF OC3IF -- IC8IF IC7IF -- INT1IF CNIF CMIF MI2C1IF SPI2IF SI2C2IF U1ERIF U3ERIF IC1IE MI2C1IE SPI2IE SI2C2IE U1ERIE U3ERIE INT0IP1 -- T3IP1 U1TXIP1 SI2C1P1 INT1IP1 -- T5IP1 SPF2IP1 -- IC6IP1 OC8IP1 -- -- -- -- LVDIP1 -- -- SI2C3P1 OC9IP1 U1TXIF U1RXIF SPI1IF SPF1IF T3IF T2IF OC2IF IC2IF -- T1IF OC1IF IC1IF -- -- -- -- -- -- -- -- -- -- INT2EP INT1EP -- -- -- -- -- -- -- -- MATHERR ADDRERR STKERR OSCFAIL -- INT0EP INT0IF SI2C1IF SPF2IF -- -- -- INT0IE SI2C1IE SPF2IE -- -- -- INT0IP0 -- T3IP0 U1TXIP0 SI2C1P0 INT1IP0 -- T5IP0 SPF2IP0 -- IC6IP0 OC8IP0 -- -- -- -- LVDIP0 -- -- SI2C3P0 U4RXIP2 U4RXIP1 U4RXIP0 OC9IP0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTERRUPT CONTROLLER REGISTER MAP
All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4440 4444 0044 4444 4404 4440 4444 0044 4440 4444 0044 0440 0440 0400 4440 0004 0040 4440 4444 4444 0044
File Name
Addr
Bit 15
Bit 14
INTCON1
0080
NSTDIS
--
INTCON2
0082
ALTIVT
DISI
IFS0
0084
--
--
IFS1
0086
U2TXIF
U2RXIF
IFS2
0088
--
--
IFS3
008A
--
RTCIF
IFS4
008C
--
--
(c) 2008 Microchip Technology Inc.
MI2C1P2 MI2C1P1 U2ERIP2 U2ERIP1 U2ERIP0 U3RXIP2 U3RXIP1 U3RXIP0 USB1IP2 USB1IP1 USB1IP0 SPF3IP2
IFS5
008E
--
--
IEC0
0094
--
--
IEC1
0096
U2TXIE
U2RXIE
IEC2
0098
--
--
IEC3
009A
--
RTCIE
IEC4
009C
--
--
IEC5
009E
--
--
IPC0
00A4
--
T1IP2
IPC1
00A6
--
T2IP2
IPC2
00A8
--
U1RXIP2 U1RXIP1 U1RXIP0
IPC3
00AA
--
--
IPC4
00AC
--
CNIP2
IPC5
00AE
--
IC8IP2
PIC24FJ256GB110 FAMILY
Preliminary
IPC6
00B0
--
T4IP2
IPC7
00B2
--
U2TXIP2
IPC8
00B4
--
--
IPC9
00B6
--
IC5IP2
IPC10
00B8
--
OC7IP2
IPC11
00BA
--
--
IPC12
00BC
--
--
IPC13
00BE
--
--
IPC15
00C2
--
--
IPC16
00C4
--
CRCIP2
IPC18
00C8
--
--
IPC19
00CA
--
--
IPC20
00CC
--
U3TXIP2
IPC21
00CE
--
U4ERIP2 U4ERIP1 U4ERIP0
IPC22
00D0
--
SPI3IP2
IPC23
00D2
--
--
DS39897B-page 37
Legend:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 3-6:
Bit 13 Timer1 Register Timer1 Period Register -- Timer2 Register Timer3 Holding Register (for 32-bit timer operations only) Timer3 Register Timer2 Period Register Timer3 Period Register -- -- Timer4 Register Timer5 Holding Register (for 32-bit operations only) Timer5 Register Timer4 Period Register Timer5 Period Register -- -- TSIDL -- -- -- -- -- -- TGATE TSIDL -- -- -- -- -- -- TGATE TCKPS1 TCKPS1 TCKPS0 TCKPS0 T32 -- -- -- TCS TCS -- -- TSIDL -- -- -- -- -- -- TGATE TCKPS1 TCKPS0 -- TSIDL -- -- -- -- -- -- TGATE TCKPS1 TCKPS0 T32 -- -- TCS TCS -- -- TSIDL -- -- -- -- -- -- TGATE TCKPS1 TCKPS0 -- TSYNC TCS -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 FFFF 0000 0000 0000 0000 FFFF FFFF 0000 0000 0000 0000 0000 FFFF FFFF 0000 0000
TIMER REGISTER MAP
File Name
Addr
Bit 15
Bit 14
TMR1
0100
PR1
0102
DS39897B-page 38
T1CON
0104
TON
TMR2
0106
TMR3HLD
0108
TMR3
010A
PR2
010C
PR3
010E
T2CON
0110
TON
T3CON
0112
TON
TMR4
0114
TMR5HLD
0116
TMR5
0118
PR4
011A
PR5
011C
T4CON
011E
TON
T5CON
0120
TON
PIC24FJ256GB110 FAMILY
Preliminary
Legend:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
(c) 2008 Microchip Technology Inc.
TABLE 3-7:
Bit 13 ICSIDL -- Input Capture 1 Buffer Register Timer Value 1 Register ICSIDL -- Input Capture 2 Buffer Register Timer Value 2 Register ICSIDL -- Input Capture 3 Buffer Register Timer Value 3 Register ICSIDL -- Input Capture 4 Buffer Register Timer Value 4 Register ICSIDL -- Input Capture 5 Buffer Register Timer Value 5 Register ICSIDL -- -- -- -- -- IC32 ICTRIG ICTSEL2 ICTSEL1 ICTSEL0 -- -- -- ICI1 TRIGSTAT ICI0 -- ICOV ICBNE ICM2 ICM1 ICM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 -- -- -- -- IC32 ICTRIG TRIGSTAT -- ICTSEL2 ICTSEL1 ICTSEL0 -- -- -- ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 -- -- -- -- IC32 ICTRIG TRIGSTAT -- ICTSEL2 ICTSEL1 ICTSEL0 -- -- -- ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 -- -- -- -- IC32 ICTRIG TRIGSTAT -- ICTSEL2 ICTSEL1 ICTSEL0 -- -- -- ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 -- -- -- -- IC32 ICTRIG TRIGSTAT -- ICTSEL2 ICTSEL1 ICTSEL0 -- -- -- ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 -- -- -- -- IC32 ICTRIG TRIGSTAT -- ICTSEL2 ICTSEL1 ICTSEL0 -- -- -- ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INPUT CAPTURE REGISTER MAP
All Resets 0000 0000 0000 xxxx 0000 0000 0000 xxxx 0000 0000 0000 xxxx 0000 0000 0000 xxxx 0000 0000 0000 xxxx 0000 0000 0000 xxxx ICI1 TRIGSTAT ICI0 -- ICOV ICBNE ICM2 ICM1 ICM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 0000 0000 0000 xxxx -- IC32 -- ICTRIG ICI1 TRIGSTAT Input Capture 8 Buffer Register Timer Value 8 Register ICSIDL -- -- -- -- ICTSEL2 ICTSEL1 ICTSEL0 -- -- -- IC32 -- ICTRIG ICI1 TRIGSTAT Input Capture 9 Buffer Register Timer Value 9 Register ICI0 -- ICOV ICBNE ICM2 ICM1 ICM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 ICI0 -- ICOV ICBNE ICM2 ICM1 ICM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 0000 0000 0000 xxxx 0000 0000 0000 xxxx
File Name SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
Addr
Bit 15
Bit 14
IC1CON1
0140
--
--
IC1CON2
0142
--
--
IC1BUF
0144
IC1TMR
0146
IC2CON1
0148
--
--
IC2CON2
014A
--
--
IC2BUF
014C
(c) 2008 Microchip Technology Inc.
Input Capture 6 Buffer Register Timer Value 6 Register ICSIDL -- -- -- -- -- IC32 ICTSEL2 ICTSEL1 ICTSEL0 -- -- -- ICTRIG Input Capture 7 Buffer Register Timer Value 7 Register ICSIDL -- -- -- -- -- ICTSEL2 ICTSEL1 ICTSEL0 --
IC2TMR
014E
IC3CON1
0150
--
--
IC3CON2
0152
--
--
IC3BUF
0154
IC3TMR
0156
IC4CON1
0158
--
--
IC4CON2
015A
--
--
IC4BUF
015C
IC4TMR
015E
IC5CON1
0160
--
--
IC5CON2
0162
--
--
IC5BUF
0164
IC5TMR
0166
PIC24FJ256GB110 FAMILY
Preliminary
IC6CON1
0168
--
--
IC6CON2
016A
--
--
IC6BUF
016C
IC6TMR
016E
IC7CON1
0170
--
--
IC7CON2
0172
--
--
IC7BUF
0174
IC7TMR
0176
IC8CON1
0178
--
--
IC8CON2
017A
--
--
IC8BUF
017C
IC8TMR
017E
IC9CON1
0180
--
--
IC9CON2
0182
--
--
IC9BUF
0184
IC9TMR
0186
DS39897B-page 39
Legend:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 3-8:
Bit 13 OCSIDL OCINV Output Compare 1 Secondary Register Output Compare 1 Register Timer Value 1 Register OCSIDL OCINV Output Compare 2 Secondary Register Output Compare 2 Register Timer Value 2 Register OCSIDL OCINV Output Compare 3 Secondary Register Output Compare 3 Register Timer Value 3 Register OCSIDL OCINV Output Compare 4 Secondary Register Output Compare 4 Register Timer Value 4 Register OCSIDL OCINV Output Compare 5 Register Timer Value 5 Register OCSIDL OCINV -- -- -- OC32 OCTSEL2 OCTSEL1 OCTSEL0 -- -- ENFLT0 OCTRIG -- TRIGSTAT -- OCTRIS OCFLT0 TRIGMODE OCM2 OCM1 OCM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 -- -- -- OC32 OCTRIG TRIGSTAT Output Compare 5 Secondary Register OCTSEL2 OCTSEL1 OCTSEL0 -- -- ENFLT0 -- -- OCTRIS OCFLT0 TRIGMODE OCM2 OCM1 OCM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 -- -- -- OC32 OCTRIG TRIGSTAT OCTRIS OCTSEL2 OCTSEL1 OCTSEL0 -- -- ENFLT0 -- -- OCFLT0 TRIGMODE OCM2 OCM1 OCM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 -- -- -- OC32 OCTRIG TRIGSTAT OCTRIS OCTSEL2 OCTSEL1 OCTSEL0 -- -- ENFLT0 -- -- OCFLT0 TRIGMODE OCM2 OCM1 OCM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 -- -- -- OC32 OCTRIG TRIGSTAT OCTRIS OCTSEL2 OCTSEL1 OCTSEL0 -- -- ENFLT0 -- -- OCFLT0 TRIGMODE OCM2 OCM1 OCM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 -- -- -- OC32 OCTRIG TRIGSTAT OCTRIS OCTSEL2 OCTSEL1 OCTSEL0 -- -- ENFLT0 -- -- OCFLT0 TRIGMODE OCM2 OCM1 OCM0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 xxxx 0000 0000 0000 0000 xxxx 0000 0000 0000 0000 xxxx 0000 0000 0000 0000 xxxx 0000 0000 0000 0000 xxxx 0000 0000 0000 0000 Timer Value 6 Register OCSIDL OCINV -- -- -- OCTSEL2 OCTSEL1 OCTSEL0 -- -- OC32 ENFLT0 OCTRIG -- TRIGSTAT Output Compare 7 Secondary Register Output Compare 7 Register Timer Value 7 Register -- OCTRIS OCFLT0 TRIGMODE OCM2 OCM1 OCM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 xxxx 0000 0000 0000 0000 xxxx
OUTPUT COMPARE REGISTER MAP
File Name
Addr
Bit 15
Bit 14
OC1CON1
0190
--
--
OC1CON2
0192
FLTMD
FLTOUT FLTTRIEN
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
DS39897B-page 40
Output Compare 6 Secondary Register Output Compare 6 Register
OC1RS
0194
OC1R
0196
OC1TMR
0198
OC2CON1
019A
--
--
OC2CON2
019C
FLTMD
FLTOUT FLTTRIEN
OC2RS
019E
OC2R
01A0
OC2TMR
01A2
OC3CON1
01A4
--
--
OC3CON2
01A6
FLTMD
FLTOUT FLTTRIEN
OC3RS
01A8
OC3R
01AA
OC3TMR
01AC
OC4CON1
01AE
--
--
OC4CON2
01B0
FLTMD
FLTOUT FLTTRIEN
OC4RS
01B2
OC4R
01B4
OC4TMR
01B6
PIC24FJ256GB110 FAMILY
Preliminary
OC5CON1
01B8
--
--
OC5CON2
01BA
FLTMD
FLTOUT FLTTRIEN
OC5RS
01BC
OC5R
01BE
OC5TMR
01C0
OC6CON1
01C2
--
--
OC6CON2
01C4
FLTMD
FLTOUT FLTTRIEN
OC6RS
01C6
OC6R
01C8
OC6TMR
01CA
OC7CON1
01CC
--
--
OC7CON2
01CE
FLTMD
FLTOUT FLTTRIEN
OC7RS
01D0
OC7R
01D2
OC7TMR
01D4
(c) 2008 Microchip Technology Inc.
Legend:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 3-8:
Bit 13 OCSIDL OCINV Output Compare 8 Secondary Register Output Compare 8 Register Timer Value 8 Register OCSIDL OCINV Output Compare 9 Secondary Register Output Compare 9 Register Timer Value 9 Register -- -- -- OC32 OCTRIG TRIGSTAT OCTRIS OCTSEL2 OCTSEL1 OCTSEL0 -- -- ENFLT0 -- -- OCFLT0 TRIGMODE OCM2 OCM1 OCM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 -- -- -- OC32 OCTRIG TRIGSTAT OCTRIS OCTSEL2 OCTSEL1 OCTSEL0 -- -- ENFLT0 -- -- OCFLT0 TRIGMODE OCM2 OCM1 OCM0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
OUTPUT COMPARE REGISTER MAP (CONTINUED)
All Resets 0000 0000 0000 0000 xxxx 0000 0000 0000 0000 xxxx
File Name
Addr
Bit 15
Bit 14
OC8CON1
01D6
--
--
OC8CON2
01D8
FLTMD
FLTOUT FLTTRIEN
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
OC8RS
01DA
OC8R
01DC
OC8TMR
01DE
OC9CON1
01E0
--
--
(c) 2008 Microchip Technology Inc.
Bit 14 -- -- -- -- -- -- -- -- -- -- I2CSIDL -- -- -- -- -- -- I2CSIDL -- -- -- -- -- -- -- -- -- SCLREL IPMIEN -- -- -- -- -- -- A10M BCL -- -- -- -- -- -- -- -- -- -- -- DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV -- -- ACKDT D/A -- -- -- -- -- BCL GCSTAT SCLREL IPMIEN A10M DISSLW -- -- -- -- SMEN ADD10 GCEN IWCOL STREN I2COV -- -- -- -- -- ACKDT D/A -- -- -- -- -- -- -- -- -- -- -- -- -- BCL GCSTAT ADD10 IWCOL -- -- -- -- -- -- -- -- -- -- -- -- -- -- I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN -- -- -- -- -- STREN I2COV -- -- -- -- -- -- ACKDT D/A -- -- -- -- -- -- Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Receive Register Transmit Register Baud Rate Generator Register ACKEN P Address Register Address Mask Register Receive Register Transmit Register Baud Rate Generator Register ACKEN P Address Register Address Mask Register Receive Register Transmit Register Baud Rate Generator Register ACKEN P Address Register Address Mask Register RCEN S PEN R/W RSEN RBF SEN TBF RCEN S PEN R/W RSEN RBF SEN TBF RCEN S PEN R/W RSEN RBF SEN TBF Bit 2 Bit 1 Bit 0
OC9CON2
01E2
FLTMD
FLTOUT FLTTRIEN
OC9RS
01E4
OC9R
01E6
OC9TMR
01E8
Legend:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 3-9:
I2CTM REGISTER MAP
All Resets 0000 00FF 0000 1000 0000 0000 0000 0000 00FF 0000 1000 0000 0000 0000 0000 00FF 0000 1000 0000 0000 0000
File Name
Addr
Bit 15
I2C1RCV
0200
--
I2C1TRN
0202
--
I2C1BRG
0204
--
PIC24FJ256GB110 FAMILY
Preliminary
I2C1CON
0206
I2CEN
I2C1STAT
0208
ACKSTAT TRSTAT
I2C1ADD
020A
--
I2C1MSK
020C
--
I2C2RCV
0210
--
I2C2TRN
0212
--
I2C2BRG
0214
--
I2C2CON
0216
I2CEN
I2C2STAT
0218
ACKSTAT TRSTAT
I2C2ADD
021A
--
I2C2MSK
021C
--
I2C3RCV
0270
--
I2C3TRN
0272
--
I2C3BRG
0274
--
I2C3CON
0276
I2CEN
I2C3STAT
0278
ACKSTAT TRSTAT
I2C3ADD
027A
--
I2C3MSK
027C
--
DS39897B-page 41
Legend:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 3-10:
Bit 13 USIDL UTXISEL0 -- -- Baud Rate Generator Prescaler Register -- UTXISEL0 -- -- -- Baud Rate Generator Prescaler Register -- UTXISEL0 -- -- -- Baud Rate Generator Prescaler Register -- UTXISEL0 -- -- Baud Rate Generator Prescaler Register -- -- -- -- -- -- -- -- -- UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN -- -- USIDL IREN RTSMD -- UEN1 UEN0 WAKE LPBACK ABAUD RXINV RIDLE BRGH PERR PDSEL1 FERR PDSEL0 OERR STSEL URXDA -- -- -- Receive Register -- -- -- Transmit Register UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE -- -- PERR -- -- USIDL IREN RTSMD -- UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 FERR PDSEL0 OERR STSEL URXDA -- -- -- Receive Register -- -- -- Transmit Register UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR -- -- -- -- USIDL IREN RTSMD -- UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 OERR STSEL URXDA -- -- -- -- Receive Register -- -- -- -- Transmit Register -- UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA IREN RTSMD -- UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0110 xxxx 0000 0000 0000 0110 xxxx 0000 0000 0000 0110 xxxx 0000 0000 0000 0110 xxxx Receive Register 0000 0000
UART REGISTER MAPS
File Name -- -- --
Addr
Bit 15
Bit 14
U1MODE
0220
UARTEN
U1STA
0222
UTXISEL1 UTXINV
DS39897B-page 42
Transmit Register Bit 13 SPISIDL -- SPIFPOL -- -- DISSCK -- -- DISSCK -- -- DISSDO -- -- -- DISSDO MODE16 -- -- -- -- -- SPISIDL -- SPIFPOL SPISIDL -- SPIFPOL DISSCK DISSDO MODE16 SMP CKE -- -- -- SPIBEC2 SPIBEC1 SPIBEC0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 SRMPT SSEN -- SRMPT CKE -- SSEN -- Transmit and Receive Buffer -- -- SPIBEC2 SPIBEC1 SPIBEC0 MODE16 -- SMP -- CKE -- SRMPT SSEN -- Transmit and Receive Buffer SPIROV CKP -- SRXMPT MSTEN -- SISEL2 SPRE2 -- SISEL1 SPRE1 -- SISEL0 SPRE0 -- SPITBF PPRE1 SPIFE SPIRBF PPRE0 SPIBEN Bit 6 SPIROV CKP -- SPIROV CKP -- Bit 5 SRXMPT MSTEN -- SRXMPT MSTEN -- Bit 4 SISEL2 SPRE2 -- SISEL2 SPRE2 -- Bit 3 SISEL1 SPRE1 -- SISEL1 SPRE1 -- Bit 2 SISEL0 SPRE0 -- SISEL0 SPRE0 -- Bit 1 SPITBF PPRE1 SPIFE SPITBF PPRE1 SPIFE Bit 0 SPIRBF PPRE0 SPIBEN SPIRBF PPRE0 SPIBEN All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -- -- Transmit and Receive Buffer -- -- SPIBEC2 SPIBEC1 SPIBEC0 SMP
U1TXREG
0224
--
U1RXREG
0226
--
U1BRG
0228
U2MODE
0230
UARTEN
U2STA
0232
UTXISEL1 UTXINV
U2TXREG
0234
--
U2RXREG
0236
--
U2BRG
0238
U3MODE
0250
UARTEN
U3STA
0252
UTXISEL1 UTXINV
U3TXREG
0254
--
U3RXREG
0256
--
U3BRG
0258
U4MODE
02B0
UARTEN
U4STA
02B2
UTXISEL1 UTXINV
U4TXREG
02B4
--
U4RXREG
02B6
--
U4BRG
02B8
PIC24FJ256GB110 FAMILY
Preliminary
Legend:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 3-11:
SPI REGISTER MAPS
File Name
Addr
Bit 15
Bit 14
SPI1STAT
0240
SPIEN
SPI1CON1
0242
--
SPI1CON2
0244
FRMEN
SPIFSD
SPI1BUF
0248
SPI2STAT
0260
SPIEN
SPI2CON1
0262
--
SPI2CON2
0264
FRMEN
SPIFSD
SPI2BUF
0268
SPI3STAT
0280
SPIEN
SPI3CON1
0282
--
SPI3CON2
0284
FRMEN
SPIFSD
SPI3BUF
0288
(c) 2008 Microchip Technology Inc.
Legend:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 3-12:
Bit 13 -- -- -- -- -- -- ODA10 ODA9 -- ODA7 ODA6 ODA5 ODA4 ODA3 ODA2 ODA1 -- -- LATA10 LATA9 -- LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 -- -- RA10 RA9 -- RA7 RA6 RA5 RA4 RA3 RA2 RA1 -- -- TRISA10 TRISA9 -- TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 RA0 LATA0 ODA0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7(2) Bit 6(2) Bit 5(2) Bit 4(2) Bit 3(2) Bit2(2) Bit 1(2) Bit 0(2)
PORTA REGISTER MAP(1)
All Resets 36FF xxxx xxxx 0000
File Name
Addr
Bit 15
Bit 14
TRISA
02C0
TRISA15 TRISA14
PORTA
02C2
RA15
RA14
LATA
02C4
LATA15
LATA14
ODCA
02C6
ODA15
ODA14
(c) 2008 Microchip Technology Inc.
Bit 13 TRISB10 RB10 LATB10 ODB10 ODB9 ODB8 ODB7 ODB6 ODB5 LATB9 LATB8 LATB7 LATB6 LATB5 RB9 RB8 RB7 RB6 RB5 RB4 LATB4 ODB4 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 TRISB3 RB3 LATB3 ODB3 Bit 2 TRISB2 RB2 LATB2 ODB2 Bit 1 TRISB1 RB1 LATB1 ODB1 Bit 0 TRISB0 RB0 LATB0 ODB0 RB13 LATB13 ODB13 ODB12 ODB11 LATB12 LATB11 RB12 RB11 Bit 13 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 -- -- -- -- Bit 4(1) TRISC4 RC4 LATC4 ODC4 Bit 3(2) TRISC3 RC3 LATC3 ODC3 Bit 2(1) TRISC2 RC2 LATC2 ODC2 Bit 1(2) TRISC1 RC1 LATC1 ODC1 Bit 0 -- -- -- -- RC13 LATC13 ODC13 ODC12 LATC12 RC12(3) Bit 13(1) Bit 11 Bit 12(1) Bit 10 Bit 9 TRISD9 RD10 LATD10 ODD11 ODD10 RD9 LATD9 ODD9 Bit 8 TRISD8 RD8 LATD8 ODD8 Bit 7 TRISD7 RD7 LATD7 ODD7 Bit 6 TRISD6 RD6 LATD6 ODD6 Bit 5 TRISD5 RD5 LATD5 ODD5 Bit 4 TRISD4 RD4 LATD4 ODD4 Bit 3 TRISD3 RD3 LATD3 ODD3 Bit 2 TRISD2 RD2 LATD2 ODD2 Bit 1 TRISD1 RD1 LATD1 ODD1 Bit 0 TRISD0 RD0 LATD0 ODD0 RD13 LATD13 ODD13 ODD12 LATD12 RD12 RD11 LATD11
Legend: Note 1: 2:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. PORTA and all associated bits are unimplemented on 64-pin devices and read as `0'. Bits are available on 80-pin and 100-pin devices only, unless otherwise noted. Bits are implemented on 100-pin devices only; otherwise read as `0'.
TABLE 3-13:
PORTB REGISTER MAP
All Resets FFFF xxxx xxxx 0000
File Name
Addr
Bit 15
Bit 14
TRISB
02C8
TRISB15 TRISB14 TRISB13 TRISB12 TRISB11
PORTB
02CA
RB15
RB14
LATB
02CC
LATB15
LATB14
ODCB
02CE
ODB15
ODB14
Legend:
Reset values are shown in hexadecimal.
TABLE 3-14:
PORTC REGISTER MAP
All Resets F01E xxxx xxxx 0000
PIC24FJ256GB110 FAMILY
Preliminary
File Name
Addr
Bit 15
Bit 14
TRISC
02D0
TRISC15 TRISC14 TRISC13 TRISC12
PORTC
02D2
RC15(3,4)
RC14
LATC
02D4
LATC15
LATC14
ODCC
02D6
ODC15
ODC14
Legend: Note 1: 2: 3: 4:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. Bits are unimplemented in 64-pin and 80-pin devices; read as `0'. Bits are unimplemented in 64-pin devices; read as `0'. RC12 and RC15 are only available when the primary oscillator is disabled or when EC mode is selected (POSCMD1:POSCMD0 Configuration bits = 11 or 00); otherwise read as `0'. RC15 is only available when POSCMD1:POSCMD0 Configuration bits = 11 or 00 and the OSCIOFN Configuration bit = 1.
TABLE 3-15:
PORTD REGISTER MAP
All Resets FFFF xxxx xxxx 0000
File Name
Addr
Bit 15(1)
Bit 14(1)
TRISD
02D8
TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10
PORTD
02DA
RD15
RD14
LATD
02DC
LATD15
LATD14
DS39897B-page 43
ODCD
02DE
ODD15
ODD14
Legend: Note 1:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. Bits are unimplemented on 64-pin devices; read as `0'.
TABLE 3-16:
Bit 13 -- -- -- -- -- -- -- ODE9 ODE8 ODE7 ODE6 ODE5 ODE4 ODE3 ODE2 ODE1 -- -- -- LATE9 LATE8 LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 -- -- -- RE9 RE8 RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 LATE0 ODE0 -- -- -- TRISE9 TRISE8 TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 Bit 12 Bit 11 Bit 10 Bit 9(1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 8(1) All Resets 03FF xxxx xxxx 0000
PORTE REGISTER MAP
File Name
Addr
Bit 15
Bit 14
TRISE
02E0
--
--
DS39897B-page 44
Bit 13(1) Bit 11 -- -- -- -- -- -- ODF8 ODF7 ODF6 ODF5 ODF4 -- -- LATF8 LATF7 LATF6 LATF5 LATF4 -- -- RF8 RF7 RF6 RF5 RF4 RF3 LATF3 ODF3 -- -- TRISF8 TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 Bit 10 Bit 9 Bit 5 Bit 4 Bit 3 TRISF13 RF13 LATF13 ODF13 ODF12 LATF12 RF12 TRISF12 Bit 12(1) Bit 8(2) Bit 7(2) Bit 6(2) Bit 2(2) TRISF2 RF2 LATF2 ODF2 Bit 1 TRISF1 RF1 LATF1 ODF1 Bit 0 TRISF0 RF0 LATF0 ODF0 All Resets 31FF xxxx xxxx 0000 Bit 13(1) Bit 11 -- -- -- -- -- ODG9 ODG8 -- LATG9 LATG8 LATG7 ODG7 -- RG9 RG8 RG7 -- TRISG9 TRISG8 TRISG7 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 TRISG6 RG6 LATG6 ODG6 Bit 12(1) Bit 5 -- -- -- -- Bit 4 -- -- -- -- Bit 3 TRISG3 RG3 LATG3 ODG3 Bit 2 TRISG2 RG2 LATG2 ODG2 Bit 1(1) TRISG1 RG1 LATG1 ODG1 Bit 0(1) TRISG0 RG0 LATG0 ODG0 All Resets F3CF xxxx xxxx 0000 RG13 LATG13 ODG13 ODG12 LATG12 RG12 Bit 13 -- -- -- -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 -- Bit 7 -- Bit 6 -- Bit 5 -- Bit 4 -- Bit 3 -- Bit 2 -- Bit 1 RTSECSEL Bit 0 PMPTTL All Resets 0000
PORTE
02E2
--
--
LATE
02E4
--
--
ODCE
02E6
--
--
Legend: Note 1:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. Bits are unimplemented in 64-pin devices; read as `0'.
TABLE 3-17:
PORTF REGISTER MAP
File Name
Addr
Bit 15
Bit 14
TRISF
02E8
--
--
PORTF
02EA
--
--
LATF
02EC
--
--
ODCF
02EE
--
--
Legend: Note 1: 2:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. Bits are unimplemented in 64-pin and 80-pin devices; read as `0'. Bits are unimplemented in 64-pin devices; read as `0'.
PIC24FJ256GB110 FAMILY
Preliminary
TABLE 3-18:
PORTG REGISTER MAP
File Name
Addr
Bit 15(1)
Bit 14(1)
TRISG
02F0
TRISG15 TRISG14 TRISG13 TRISG12
PORTG
02F2
RG15
RG14
LATG
02F4
LATG15
LATG14
ODCG
02F6
ODG15
ODG14
Legend: Note 1:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. Bits are unimplemented in 64-pin and 80-pin devices; read as `0'.
TABLE 3-19:
PAD CONFIGURATION REGISTER MAP
File Name
Addr
Bit 15
Bit 14
PADCFG1
02FC
--
--
(c) 2008 Microchip Technology Inc.
Legend:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 3-20:
Bit 13 ADC Data Buffer 0 ADC Data Buffer 1 ADC Data Buffer 2 ADC Data Buffer 3 ADC Data Buffer 4 ADC Data Buffer 5 ADC Data Buffer 6 ADC Data Buffer 7 ADC Data Buffer 8 ADC Data Buffer 9 ADC Data Buffer 10 ADC Data Buffer 11 ADC Data Buffer 12 ADC Data Buffer 13 ADC Data Buffer 14 ADC Data Buffer 15 -- VCFG0 r ADCS7 CH0NA -- PCFG7 CSSL7 -- -- -- PCFG6 CSSL6 -- -- -- PCFG13 CSSL13 -- -- -- -- -- -- CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 -- -- -- -- -- CH0SB4 CH0SB3 CH0SB2 CH0SB1 CH0SB0 SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 ADCS6 r -- CSCNA -- -- BUFS -- r -- -- ADSIDL -- -- -- FORM1 FORM0 SSRC2 SSRC1 SSRC0 SMPI3 ADCS5 -- -- PCFG5 CSSL5 -- -- SMPI2 ADCS4 CH0SA4 -- PCFG4 CSSL4 -- -- SMPI1 ADCS3 CH0SA3 -- PCFG3 CSSL3 -- ASAM SMPI0 ADCS2 CH0SA2 -- PCFG2 CSSL2 -- SAMP BUFM ADCS1 CH0SA1 PCFG17 PCFG1 CSSL1 CSS17 DONE ALTS ADCS0 CH0SA0 PCFG16 PCFG0 CSSL0 CSS16 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ADC REGISTER MAP
All Resets xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000
File Name
Addr
Bit 15
Bit 14
ADC1BUF0
0300
ADC1BUF1
0302
ADC1BUF2
0304
ADC1BUF3
0306
ADC1BUF4
0308
ADC1BUF5
030A
(c) 2008 Microchip Technology Inc.
-- Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 -- -- -- -- -- -- -- --
ADC1BUF6
030C
ADC1BUF7
030E
ADC1BUF8
0310
ADC1BUF9
0312
ADC1BUFA
0314
ADC1BUFB
0316
ADC1BUFC
0318
ADC1BUFD
031A
ADC1BUFE
031C
ADC1BUFF
031E
AD1CON1
0320
ADON
AD1CON2
0322
VCFG2
VCFG1
AD1CON3
0324
ADRC
AD1CHS0
0328
CH0NB
PIC24FJ256GB110 FAMILY
Preliminary
AD1PCFGH
032A
--
AD1PCFGL
032C
PCFG15
PCFG14
AD1CSSL
0330
CSSL15
CSSL14
AD1CSSH
0332
--
Legend:
-- = unimplemented, read as `0', r = reserved, maintain as `0'. Reset values are shown in hexadecimal.
TABLE 3-21:
CTMU REGISTER MAP
All Resets 0000 0000
File Name
Addr
Bit 15
Bit 14
CTMUCON
033C CTMUEN
--
CTMUICON 033E
ITRIM5
ITRIM4
Legend:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
DS39897B-page 45
TABLE 3-22:
Bit 13 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- UTEYE UOEMON -- -- -- -- -- -- -- -- -- -- -- -- PID3 PID2 PID1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- LSPDEN(1) -- -- -- -- -- JSTATE(1) SE0 TOKBUSY RESET -- -- -- -- -- -- SE0 PKTDIS -- -- -- -- -- -- ENDPT3 ENDPT2 ENDPT1 ENDPT0 -- -- -- -- -- BTSEE -- DMAEE BTOEE DFN8EE DIR HOSTEN HOSTEN -- -- -- -- -- BTSEE -- DMAEE BTOEE DFN8EE -- -- -- -- -- BTSEF -- DMAEF BTOEF DFN8EF -- -- -- -- -- BTSEF -- DMAEF BTOEF DFN8EF -- -- -- -- -- STALLIE ATTACHIE(1) RESUMEIE IDLEIE TRNIE SOFIE CRC16EF CRC16EF CRC16EE CRC16EE PPBI RESUME RESUME -- -- -- -- -- STALLIE -- RESUMEIE IDLEIE TRNIE SOFIE -- -- -- -- -- STALLIF ATTACHIF(1) RESUMEIF IDLEIF TRNIF SOFIF -- -- -- -- -- STALLIF -- RESUMEIF IDLEIF TRNIF SOFIF UERRIF UERRIF UERRIE UERRIE CRC5EF EOFEF(1) CRC5EE EOFEE(1) -- PPBRST PPBRST -- -- -- -- -- UACTPND -- -- USLPGRD -- -- USUSPND -- -- -- -- -- DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG -- -- -- -- -- ID -- LSTATE -- SESVD SESEND -- -- -- -- -- -- IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE -- VBUSVD VBUSDIS USBPWR URSTIF DETACHIF(1) URSTIE PIDEF PIDEF PIDEE PIDEE -- USBEN SOFEN(1) -- -- -- -- -- -- IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF -- VBUSVDIF VBUSVDIE Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 DETACHIE(1) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 PID0 USBSIDL PUVBUS EP3 Start-Of-Frame Count Register -- -- PPB1 EXTI2CEN UVBUSDIS UVCMPDIS PPB0 UTRDIS EP2 EP1 EP0 0000 0000 0000 0000
USB OTG REGISTER MAP
File Name
Addr
Bit 15
Bit 14
U1OTGIR
0480
--
--
U1OTGIE
0482
--
--
DS39897B-page 46
USB Device Address (DEVADDR) Register Buffer Descriptor Table Base Address Register Frame Count Register Low Byte Frame Count Register High Byte
U1OTGSTAT
0484
--
--
U1OTGCON
0486
--
--
U1PWRC
0488
--
--
U1IR
048A(1)
--
--
--
--
U1IE
048C(1)
--
--
--
--
U1EIR
048E(1)
--
--
--
--
U1EIE
0490(1)
--
--
--
--
U1STAT
0492
--
--
U1CON
0494(1)
--
--
--
--
U1ADDR
0496
--
--
U1BDTP1
0498
--
--
U1FRML
049A
--
--
U1FRMH
049C
--
--
PIC24FJ256GB110 FAMILY
Preliminary
U1TOK(2)
049E
--
--
U1SOF(2)
04A0
--
--
U1CNFG1
04A6
--
--
U1CNFG2
04A8
--
--
Legend: Note 1: 2:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Alternate register or bit definitions when the module is operating in Host mode. This register is available in Host mode only.
(c) 2008 Microchip Technology Inc.
TABLE 3-22:
Bit 13 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- USB Power Supply PWM Duty Cycle Register -- -- -- -- PWMPOL CNTEN -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPCONDIS -- -- -- -- -- -- -- -- -- EPCONDIS -- -- -- -- -- -- -- -- EPCONDIS -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN -- -- -- -- -- -- -- -- EPCONDIS EPRXEN -- -- -- -- -- -- -- -- EPCONDIS EPRXEN -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL -- -- -- -- -- LSPD(1) -- EPCONDIS EPRXEN EPTXEN EPSTALL RETRYDIS(1) EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
USB OTG REGISTER MAP (CONTINUED)
File Name
Addr
Bit 15
Bit 14
U1EP0
04AA
--
--
U1EP1
04AC
--
--
U1EP2
04AE
--
--
U1EP3
04B0
--
--
U1EP4
04B2
--
--
U1EP5
04B4
--
--
U1EP6
04B6
--
--
(c) 2008 Microchip Technology Inc.
USB Power Supply PWM Period Register Bit 13 PSIDL IRQM0 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 INCM1 INCM0 MODE16 MODE1 ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN MODE0 ADDR8 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 CSF1 WAITB1 ADDR7 Bit 6 CSF0 WAITB0 ADDR6 Bit 5 ALP WAITM3 ADDR5 Bit 4 CS2P WAITM2 ADDR4 Bit 3 CS1P WAITM1 ADDR3 Bit 2 BEP WAITM0 ADDR2 Bit 1 WRSP WAITE1 ADDR1 Bit 0 RDSP WAITE0 ADDR0 Parallel Port Data Out Register 1 (Buffers 0 and 1) Parallel Port Data Out Register 2 (Buffers 2 and 3) Parallel Port Data In Register 1 (Buffers 0 and 1) Parallel Port Data In Register 2 (Buffers 2 and 3) PTEN13 -- -- IB3F PTEN12 PTEN11 PTEN10 IB2F PTEN9 IB1F PTEN8 IB0F PTEN7 OBE PTEN6 OBUF PTEN5 -- PTEN4 -- PTEN3 OB3E PTEN2 OB2E PTEN1 OB1E PTEN0 OB0E
U1EP7
04B8
--
--
U1EP8
04BA
--
--
U1EP9
04BC
--
--
U1EP10
04BE
--
--
U1EP11
04C0
--
--
U1EP12
04C2
--
--
U1EP13
04C4
--
--
U1EP14
04C6
--
--
U1EP15
04C8
--
--
U1PWMRRS
04CC
U1PWMCON
04CE
PWMEN
--
PIC24FJ256GB110 FAMILY
Preliminary
Legend: Note 1: 2:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Alternate register or bit definitions when the module is operating in Host mode. This register is available in Host mode only.
TABLE 3-23:
PARALLEL MASTER/SLAVE PORT REGISTER MAP
All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000
File Name Addr
Bit 15
Bit 14
PMCON
0600
PMPEN
--
PMMODE
0602
BUSY
IRQM1
PMADDR
0604
CS2
CS1
PMDOUT1
PMDOUT2 0606
PMDIN1
0608
PMDIN2
060A
PMAEN
060C
PTEN15
PTEN14
PMSTAT
060E
IBF
IBOV
DS39897B-page 47
Legend:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 3-24:
Bit 13 Alarm Value Register Window Based on ALRMPTR<1:0> AMASK3 RTCC Value Register Window Based on RTCPTR<1:0> RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx 0000 xxxx 0000
REAL-TIME CLOCK AND CALENDAR REGISTER MAP
File Name
Addr
Bit 15
Bit 14
ALRMVAL
0620
ALCFGRPT
0622
ALRMEN
CHIME
DS39897B-page 48
Bit 13 -- -- CPOL -- -- -- -- -- CEVT COUT EVPOL1 EVPOL0 -- CREF -- -- CEVT COUT EVPOL1 EVPOL0 -- CREF -- -- CEVT COUT EVPOL1 EVPOL0 -- CREF CPOL CPOL -- -- -- -- -- -- -- -- CVREN CVROE CVRR CVRSS CVR3 -- C3EVT C2EVT C1EVT -- -- -- -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 C3OUT CVR2 -- -- -- Bit 1 C2OUT CVR1 CCH1 CCH1 CCH1 Bit 0 C1OUT CVR0 CCH0 CCH0 CCH0 All Resets 0000 0000 0000 0000 0000 -- -- COE COE COE Bit 13 CSIDL X13 CRC Data Input Register CRC Result Register X12 X11 X10 X9 X8 X7 X6 VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 -- X5 Bit 4 CRCGO X4 Bit 3 PLEN3 X3 Bit 2 PLEN2 X2 Bit 1 PLEN1 X1 Bit 0 PLEN0 -- All Resets 0040 0000 0000 0000 --
RTCVAL
0624
RCFGCAL
0626
RTCEN
--
Legend:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 3-25:
COMPARATORS REGISTER MAP
File Name
Addr
Bit 15
Bit 14
CMSTAT
0630
CMIDL
CVRCON
0632
--
CM1CON
0634
CON
CM2CON
0636
CON
CM3CON
0638
CON
Legend:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 3-26:
CRC REGISTER MAP
File Name
Addr
Bit 15
Bit 14
PIC24FJ256GB110 FAMILY
Preliminary
CRCCON
0640
--
CRCXOR
0642
X15
X14
CRCDAT
0644
CRCWDAT
0646
Legend:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
(c) 2008 Microchip Technology Inc.
TABLE 3-27:
Bit 13 INT1R5 INT3R5 T1CKR5 T3CKR5 T5CKR5 IC2R5 IC4R5 IC6R5 IC8R5 OCFBR5 IC9R5 U3RXR5 U1CTSR5 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 U2CTSR5 U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0 SCK1R5 U3CTSR5 U3CTSR4 U3CTSR3 U3CTSR2 U3CTSR1 U3CTSR0 SCK2R5 -- U4CTSR5 U4CTSR4 U4CTSR3 U4CTSR2 U4CTSR1 U4CTSR0 SCK3R5 -- RP1R5 RP3R5 RP5R5(1) RP7R5 RP9R5 RP11R5 RP13R5 RP17R5 RP19R5 RP21R5 RP23R5 RP25R5 RP27R5 RP29R5 RP29R4 RP29R3 RP27R4 RP27R3 RP25R4 RP25R3 RP23R4 RP23R3 RP21R4 RP21R3 RP21R2 RP23R2 RP25R2 RP27R2 RP29R2 RP19R4 RP19R3 RP19R2 RP17R4 RP17R3 RP17R2 RP17R1 RP19R1 RP21R1 RP23R1 RP25R1 RP27R1 RP29R1 RP13R4 RP13R3 RP13R2 RP13R1 RP11R4 RP11R3 RP11R2 RP11R1 RP9R4 RP9R3 RP9R2 RP9R1 RP9R0 RP11R0 RP13R0 RP17R0 RP19R0 RP21R0 RP23R0 RP25R0 RP27R0 RP29R0 RP7R4 RP7R3 RP7R2 RP7R1 RP7R0 RP5R4(1) RP5R3(1) RP5R2(1) RP5R1(1) RP5R0(1) RP3R4 RP3R3 RP3R2 RP3R1 RP3R0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 -- -- -- -- -- -- -- SCK3R4 SCK3R3 SCK3R2 SCK3R1 SCK3R0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0 -- -- -- -- SS1R5 SDI2R5 SS2R5 U4RXR5 SDI3R5 SS3R5 RP0R5 RP2R5 RP4R5 RP6R5 RP8R5 RP10R5 RP12R5 RP14R5 RP16R5 RP18R5 RP20R5 RP22R5 RP24R5 RP26R5 RP28R5 RP30R5 SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 -- -- SDI1R5 -- -- U2RXR5 -- -- U1RXR5 U1RXR4 U2RXR4 SDI1R4 SS1R4 SDI2R4 SS2R4 U4RXR4 SDI3R4 SS3R4 RP0R4 RP2R4 RP4R4 RP6R4 RP8R4 RP10R4 RP12R4 RP14R4 RP16R4 RP18R4 RP20R4 RP22R4 RP24R4 RP26R4 RP28R4 RP30R4 U3RXR4 U3RXR3 U3RXR2 U3RXR1 U3RXR0 -- -- -- -- IC9R4 IC9R3 IC9R2 IC9R1 IC9R0 -- -- -- -- -- -- U1RXR3 U2RXR3 SDI1R3 SS1R3 SDI2R3 SS2R3 U4RXR3 SDI3R3 SS3R3 RP0R3 RP2R3 RP4R3 RP6R3 RP8R3 RP10R3 RP12R3 RP14R3 RP16R3 RP18R3 RP20R3 RP22R3 RP24R3 RP26R3 RP28R3 RP30R3 OCFBR4 OCFBR3 OCFBR2 OCFBR1 OCFBR0 -- -- OCFAR5 OCFAR4 OCFAR3 IC8R4 IC8R3 IC8R2 IC8R1 IC8R0 -- -- IC7R5 IC7R4 IC7R3 IC6R4 IC6R3 IC6R2 IC6R1 IC6R0 -- -- IC5R5 IC5R4 IC5R3 IC4R4 IC4R3 IC4R2 IC4R1 IC4R0 -- -- IC3R5 IC3R4 IC3R3 IC3R2 IC5R2 IC7R2 OCFAR2 -- -- U1RXR2 U2RXR2 SDI1R2 SS1R2 SDI2R2 SS2R2 U4RXR2 SDI3R2 SS3R2 RP0R2 RP2R2 RP4R2 RP6R2 RP8R2 RP10R2 RP12R2 RP14R2 RP16R2 RP18R2 RP20R2 RP22R2 RP24R2 RP26R2 RP28R2 RP30R2 IC2R4 IC2R3 IC2R2 IC2R1 IC2R0 -- -- IC1R5 IC1R4 IC1R3 IC1R2 T5CKR4 T5CKR3 T5CKR2 T5CKR1 T5CKR0 -- -- T4CKR5 T4CKR4 T4CKR3 T4CKR2 T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0 -- -- T2CKR5 T2CKR4 T2CKR3 T2CKR2 T1CKR4 T1CKR3 T1CKR2 T1CKR1 T1CKR0 -- -- INT4R5 INT4R4 INT4R3 INT4R2 INT4R1 T2CKR1 T4CKR1 IC1R1 IC3R1 IC5R1 IC7R1 OCFAR1 -- -- U1RXR1 U2RXR1 SDI1R1 SS1R1 SDI2R1 SS2R1 U4RXR1 SDI3R1 SS3R1 RP0R1 RP2R1 RP4R1 RP6R1 RP8R1 RP10R1 RP12R1 RP14R1 RP16R1 RP18R1 RP20R1 RP22R1 RP24R1 RP26R1 RP28R1 RP30R1 INT3R4 INT3R3 INT3R2 INT3R1 INT3R0 -- -- INT2R5 INT2R4 INT2R3 INT2R2 INT2R1 INT1R4 INT1R3 INT1R2 INT1R1 INT1R0 -- -- -- -- -- -- -- -- INT2R0 INT4R0 T2CKR0 T4CKR0 IC1R0 IC3R0 IC5R0 IC7R0 OCFAR0 -- -- U1RXR0 U2RXR0 SDI1R0 SS1R0 SDI2R0 SS2R0 U4RXR0 SDI3R0 SS3R0 RP0R0 RP2R0 RP4R0 RP6R0 RP8R0 RP10R0 RP12R0 RP14R0 RP16R0 RP18R0 RP20R0 RP22R0 RP24R0 RP26R0 RP28R0 RP30R0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PERIPHERAL PIN SELECT REGISTER MAP
All Resets 3F00 3F3F 3F3F 3F3F 3F3F 3F3F 3F3F 3F3F 3F3F 3F3F 3F00 3F00 3F3F 3F3F 3F3F 3F3F 3F3F 003F 3F3F 3F3F 003F 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
File Name
Addr
Bit 15
Bit 14
RPINR0
0680
--
--
RPINR1
0682
--
--
RPINR2
0684
--
--
RPINR3
0686
--
--
RPINR4
0688
--
--
RPINR7
068E
--
--
(c) 2008 Microchip Technology Inc.
RP15R5(1) RP15R4(1) RP15R3(1) RP15R2(1) RP15R1(1) RP15R0(1) RP31R5(2) RP31R4(2) RP31R3(2) RP31R2(2) RP31R1(2) RP31R0(2)
RPINR8
0690
--
--
RPINR9
0692
--
--
RPINR10
0694
--
--
RPINR11
0696
--
--
RPINR15
069E
--
--
RPINR17
06A2
--
--
RPINR18
06A4
--
--
RPINR19
06A6
--
--
RPINR20
06A8
--
--
RPINR21
06AA
--
--
RPINR22
06AC
--
--
RPINR23
06AE
--
--
RPINR27
06B6
--
--
RPINR28
06B8
--
--
PIC24FJ256GB110 FAMILY
Preliminary
RPINR29
06BA
--
--
RPOR0
06C0
--
--
RPOR1
06C2
--
--
RPOR2
06C4
--
--
RPOR3
06C6
--
--
RPOR4
06C8
--
--
RPOR5
06CA
--
--
RPOR6
06CC
--
--
RPOR7
06CE
--
--
RPOR8
06D0
--
--
RPOR9
06D2
--
--
RPOR10
06D4
--
--
RPOR11
06D6
--
--
RPOR12
06D8
--
--
RPOR13
06DA
--
--
RPOR14
06DC
--
--
DS39897B-page 49
RPOR15
06DE
--
--
Legend: Note 1: 2:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Bits are unimplemented in 64-pin devices; read as `0'. Bits are unimplemented in 64-pin and 80-pin devices; read as `0'.
TABLE 3-28:
Bit 13 -- COSC1 DOZE1 -- ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- TUN5 TUN4 TUN3 TUN2 TUN1 DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0 CPDIV1 CPDIV0 -- -- -- -- -- -- TUN0 -- COSC0 -- NOSC2 NOSC1 NOSC0 CLKLOCK IOLOCK LOCK -- CF POSCEN SOSCEN OSWEN -- -- -- CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets Note 1 Note 2 0100 0000 0000
SYSTEM REGISTER MAP
File Name
Addr
Bit 15
Bit 14
RCON
0740
TRAPR
IOPUWR
OSCCON -- --
0742
--
COSC2
DS39897B-page 50
Bit 13 WRERR -- -- -- -- -- -- -- -- -- -- -- ERASE -- -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000(1) 0000 NVMKEY Register<7:0> Bit 13 T3MD IC6MD -- -- -- -- -- -- -- -- -- -- -- -- -- IC9MD -- -- -- -- -- -- -- -- -- -- CMPMD RTCCMD PMPMD CRCMD IC5MD IC4MD IC3MD IC2MD IC1MD OC8MD T2MD T1MD -- -- -- I2C1MD U2MD OC7MD -- UPWMMD -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 U1MD OC6MD -- U4MD -- -- Bit 4 SPI2MD OC5MD -- -- -- -- Bit 3 SPI1MD OC4MD U3MD -- -- Bit 2 -- OC3MD I2C3MD REFOMD CTMUMD -- -- Bit 1 -- OC2MD I2C2MD LVDMD -- -- Bit 0 ADC1MD OC1MD -- USB1MD OC9MD SPI3MD All Resets 0000 0000 0000 0000 0000 0000 -- -- -- --
CLKDIV
0744
ROI
DOZE2
OSCTUN
0748
--
REFOCON
074E
ROEN
Legend: Note 1: 2:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal. The Reset value of the RCON register is dependent on the type of Reset event. See Section 5.0 "Resets" for more information. The Reset value of the OSCCON register is dependent on both the type of Reset event and the device configuration. See Section 7.0 "Oscillator Configuration" for more information.
TABLE 3-29:
NVM REGISTER MAP
File Name
Addr
Bit 15
Bit 14
NVMCON
0760
WR
WREN
NVMKEY
0766
--
--
Legend: Note 1:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
TABLE 3-30:
PMD REGISTER MAP
PIC24FJ256GB110 FAMILY
Preliminary
File Name
Addr
Bit 15
Bit 14
PMD1
0770
T5MD
T4MD
PMD2
0772
IC8MD
IC7MD
PMD3
0774
--
PMD4
0776
--
PMD5
0778
--
PMD6
077A
--
Legend:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
(c) 2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
3.2.5 SOFTWARE STACK
3.3
In addition to its use as a working register, the W15 register in PIC24F devices is also used as a Software Stack Pointer. The pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 3-4. Note that for a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear. Note: A PC push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push.
Interfacing Program and Data Memory Spaces
The PIC24F architecture uses a 24-bit wide program space and 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. Aside from normal execution, the PIC24F architecture provides two methods by which program space can be accessed during operation: * Using table instructions to access individual bytes or words anywhere in the program space * Remapping a portion of the program space into the data space (program space visibility) Table instructions allow an application to read or write to small areas of the program memory. This makes the method ideal for accessing data tables that need to be updated from time to time. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look ups from a large table of static data. It can only access the least significant word of the program word.
The Stack Pointer Limit Value register (SPLIM), associated with the Stack Pointer, sets an upper address boundary for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM<0> is forced to `0' because all stack operations must be word-aligned. Whenever an EA is generated using W15 as a source or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal, and a push operation is performed, a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. Thus, for example, if it is desirable to cause a stack error trap when the stack grows beyond address 2000h in RAM, initialize the SPLIM with the value, 1FFEh. Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to be less than 0800h. This prevents the stack from interfering with the Special Function Register (SFR) space. A write to the SPLIM register should not be immediately followed by an indirect read operation using W15.
3.3.1
ADDRESSING PROGRAM SPACE
Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. For table operations, the 8-bit Table Memory Page Address register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG<7> = 0) or the configuration memory (TBLPAG<7> = 1). For remapping operations, the 8-bit Program Space Visibility Page Address register (PSVPAG) is used to define a 16K word page in the program space. When the Most Significant bit of the EA is `1', PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program space address. Unlike table operations, this limits remapping operations strictly to the user memory area. Table 3-31 and Figure 3-5 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P<23:0> refers to a program space word, whereas D<15:0> refers to a data space word.
FIGURE 3-4:
0000h 15
CALL STACK FRAME
0
Stack Grows Towards Higher Address
PC<15:0> 000000000 PC<22:16>
W15 (before CALL) W15 (after CALL) POP : [--W15] PUSH : [W15++]
(c) 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 51
PIC24FJ256GB110 FAMILY
TABLE 3-31: PROGRAM SPACE ADDRESS CONSTRUCTION
Access Space User User Configuration Program Space Visibility (Block Remap/Read) Note 1: User 0 0 Program Space Address <23> 0 TBLPAG<7:0> 0xxx xxxx TBLPAG<7:0> 1xxx xxxx PSVPAG<7:0> xxxx xxxx <22:16> <15> PC<22:1> 0xx xxxx xxxx xxxx xxxx xxx0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<14:0>(1) xxx xxxx xxxx xxxx <14:1> <0> 0 Access Type Instruction Access (Code Execution) TBLRD/TBLWT (Byte/Word Read/Write)
Data EA<15> is always `1' in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>.
FIGURE 3-5:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
0
Program Counter 23 Bits EA
0
1/0
Table Operations(2)
1/0
TBLPAG 8 Bits 24 Bits 16 Bits
Select Program Space Visibility(1) (Remapping) 0 PSVPAG 8 Bits
1
EA
0
15 Bits 23 Bits
User/Configuration Space Select
Byte Select
Note 1: The LSb of program space addresses is always fixed as `0' in order to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space.
DS39897B-page 52
Preliminary
(c) 2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
3.3.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS
2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P<23:16>) to a data address. Note that D<15:8>, the `phantom' byte, will always be `0'. In Byte mode, it maps the upper or lower byte of the program word to D<7:0> of the data address, as above. Note that the data will always be `0' when the upper `phantom' byte is selected (byte select = 1).
The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two, 16-bit word-wide address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space which contains the least significant data word, and TBLRDH and TBLWTH access the space which contains the upper data byte. Two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. Both function as either byte or word operations. 1. TBLRDL (Table Read Low): In Word mode, it maps the lower word of the program space location (P<15:0>) to a data address (D<15:0>). In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when byte select is `1'; the lower byte is selected when it is `0'.
In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 4.0 "Flash Program Memory". For all table operations, the area of program memory space to be accessed is determined by the Table Memory Page Address register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user and configuration spaces. When TBLPAG<7> = 0, the table page is located in the user memory space. When TBLPAG<7> = 1, the page is located in configuration space. Note: Only table read operations will execute in the configuration memory space, and only then, in implemented areas such as the Device ID. Table write operations are not allowed.
FIGURE 3-6:
TBLPAG 02
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
Data EA<15:0> 23 15 0 000000h 00000000 020000h 030000h 00000000 00000000 00000000 `Phantom' Byte 23 16 8 0
TBLRDH.B (Wn<0> = 0) TBLRDL.B (Wn<0> = 1) TBLRDL.B (Wn<0> = 0) TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in the user memory area.
800000h
(c) 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 53
PIC24FJ256GB110 FAMILY
3.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY
24-bit program word are used to contain the data. The upper 8 bits of any program space locations used as data should be programmed with `1111 1111' or `0000 0000' to force a NOP. This prevents possible issues should the area of code ever be accidentally executed. Note: PSV access is temporarily disabled during table reads/writes.
The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., TBLRDL/H). Program space access through the data space occurs if the Most Significant bit of the data space EA is `1', and program space visibility is enabled by setting the PSV bit in the CPU Control register (CORCON<2>). The location of the program memory space to be mapped into the data space is determined by the Program Space Visibility Page Address register (PSVPAG). This 8-bit register defines any one of 256 possible pages of 16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory address, with the 15 bits of the EA functioning as the lower bits. Note that by incrementing the PC by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses. Data reads to this area add an additional cycle to the instruction being executed, since two program memory fetches are required. Although each data space address, 8000h and higher, maps directly into a corresponding program memory address (see Figure 3-7), only the lower 16 bits of the
For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV.D instructions will require one instruction cycle in addition to the specified execution time. All other instructions will require two instruction cycles in addition to the specified execution time. For operations that use PSV which are executed inside a REPEAT loop, there will be some instances that require two instruction cycles in addition to the specified execution time of the instruction: * Execution in the first iteration * Execution in the last iteration * Execution prior to exiting the loop due to an interrupt * Execution upon re-entering the loop after an interrupt is serviced Any other iteration of the REPEAT loop will allow the instruction accessing data, using PSV, to execute in a single cycle.
FIGURE 3-7:
PROGRAM SPACE VISIBILITY OPERATION
When CORCON<2> = 1 and EA<15> = 1:
Program Space
PSVPAG 02 23 15 0 000000h 010000h 018000h The data in the page designated by PSVPAG is mapped into the upper half of the data memory space....
Data Space
0000h Data EA<14:0>
8000h
PSV Area ...while the lower 15 bits of the EA specify an exact address within the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address.
FFFFh
800000h
DS39897B-page 54
Preliminary
(c) 2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
4.0
Note:
FLASH PROGRAM MEMORY
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 4. Program Memory" (DS39715).
RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may write program memory data in blocks of 64 instructions (192 bytes) at a time, and erase program memory in blocks of 512 instructions (1536 bytes) at a time.
4.1
Table Instructions and Flash Programming
The PIC24FJ256GB110 family of devices contains internal Flash program memory for storing and executing application code. It can be programmed in four ways: * * * * In-Circuit Serial ProgrammingTM (ICSPTM) Run-Time Self-Programming (RTSP) JTAG Enhanced In-Circuit Serial ProgrammingTM (Enhanced ICSPTM)
Regardless of the method used, all programming of Flash memory is done with the table read and table write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using the TBLPAG<7:0> bits and the Effective Address (EA) from a W register specified in the table instruction, as shown in Figure 4-1. The TBLRDL and the TBLWTL instructions are used to read or write to bits<15:0> of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes. The TBLRDH and TBLWTH instructions are used to read or write to bits<23:16> of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode.
ICSP allows a PIC24FJ256GB110 family device to be serially programmed while in the end application circuit. This is simply done with two lines for the programming clock and programming data (which are named PGECx and PGEDx, respectively), and three other lines for power (VDD), ground (VSS) and Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.
FIGURE 4-1:
ADDRESSING FOR TABLE REGISTERS
24 Bits Using Program Counter 0 Program Counter 0
Working Reg EA Using Table Instruction 1/0 TBLPAG Reg 8 Bits 16 Bits
User/Configuration Space Select
24-Bit EA
Byte Select
(c) 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 55
PIC24FJ256GB110 FAMILY
4.2 RTSP Operation 4.3 JTAG Operation
The PIC24F Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase blocks of eight rows (512 instructions) at a time and to program one row at a time. It is also possible to program single words. The 8-row erase blocks and single row write blocks are edge-aligned, from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively. When data is written to program memory using TBLWT instructions, the data is not written directly to memory. Instead, data written using table writes is stored in holding latches until the programming sequence is executed. Any number of TBLWT instructions can be executed and a write will be successfully performed. However, 64 TBLWT instructions are required to write the full row of memory. To ensure that no data is corrupted during a write, any unused addresses should be programmed with FFFFFFh. This is because the holding latches reset to an unknown state, so if the addresses are left in the Reset state, they may overwrite the locations on rows which were not rewritten. The basic sequence for RTSP programming is to set up a Table Pointer, then do a series of TBLWT instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. Data can be loaded in any order and the holding registers can be written to multiple times before performing a write operation. Subsequent writes, however, will wipe out any previous writes. Note: Writing to a location multiple times without erasing is not recommended. The PIC24F family supports JTAG programming and boundary scan. Boundary scan can improve the manufacturing process by verifying pin-to-PCB connectivity. Programming can be performed with industry standard JTAG programmers supporting Serial Vector Format (SVF).
4.4
Enhanced In-Circuit Serial Programming
Enhanced In-Circuit Serial Programming uses an on-board bootloader, known as the program executive, to manage the programming process. Using an SPI data frame format, the program executive can erase, program and verify program memory. For more information on Enhanced ICSP, see the device programming specification.
4.5
Control Registers
There are two SFRs used to read and write the program Flash memory: NVMCON and NVMKEY. The NVMCON register (Register 4-1) controls which blocks are to be erased, which memory type is to be programmed and when the programming cycle starts. NVMKEY is a write-only register that is used for write protection. To start a programming or erase sequence, the user must consecutively write 55h and AAh to the NVMKEY register. Refer to Section 4.6 "Programming Operations" for further details.
4.6
Programming Operations
All of the table write operations are single-word writes (2 instruction cycles), because only the buffers are written. A programming cycle is required for programming each row.
A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. During a programming or erase operation, the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the operation and the WR bit is automatically cleared when the operation is finished.
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REGISTER 4-1:
R/SO-0(1) WR bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 SO = Set Only bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0(1) ERASE U-0 -- U-0 -- R/W-0(1) NVMOP3(2) R/W-0(1) NVMOP2(2) R/W-0(1) NVMOP1(2)
NVMCON: FLASH MEMORY CONTROL REGISTER
R/W-0(1) WRERR U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0(1) NVMOP0(2) bit 0 WREN
R/W-0(1)
WR: Write Control bit(1) 1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. 0 = Program or erase operation is complete and inactive WREN: Write Enable bit(1) 1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations WRERR: Write Sequence Error Flag bit(1) 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally Unimplemented: Read as `0' ERASE: Erase/Program Enable bit(1) 1 = Perform the erase operation specified by NVMOP3:NVMOP0 on the next WR command 0 = Perform the program operation specified by NVMOP3:NVMOP0 on the next WR command Unimplemented: Read as `0' NVMOP3:NVMOP0: NVM Operation Select bits(1,2) 1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)(3) 0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1) 0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0) 0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1) These bits can only be reset on POR. All other combinations of NVMOP3:NVMOP0 are unimplemented. Available in ICSPTM mode only. Refer to device programming specification.
bit 14
bit 13
bit 12-7 bit 6
bit 5-4 bit 3-0
Note 1: 2: 3:
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4.6.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY
4. 5. The user can program one row of Flash program memory at a time. To do this, it is necessary to erase the 8-row erase block containing the desired row. The general process is: 1. 2. 3. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase the block (see Example 4-1): a) Set the NVMOP bits (NVMCON<3:0>) to `0010' to configure for block erase. Set the ERASE (NVMCON<6>) and WREN (NVMCON<14>) bits. b) Write the starting address of the block to be erased into the TBLPAG and W registers. c) Write 55h to NVMKEY. d) Write AAh to NVMKEY. e) Set the WR bit (NVMCON<15>). The erase cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is done, the WR bit is cleared automatically. Write the first 64 instructions from data RAM into the program memory buffers (see Example 4-1). Write the program block to Flash memory: a) Set the NVMOP bits to `0001' to configure for row programming. Clear the ERASE bit and set the WREN bit. b) Write 55h to NVMKEY. c) Write AAh to NVMKEY. d) Set the WR bit. The programming cycle begins and the CPU stalls for the duration of the write cycle. When the write to Flash memory is done, the WR bit is cleared automatically. Repeat steps 4 and 5, using the next available 64 instructions from the block in data RAM by incrementing the value in TBLPAG, until all 512 instructions are written back to Flash memory.
6.
For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example 4-3.
EXAMPLE 4-1:
ERASING A PROGRAM MEMORY BLOCK
; ; Initialize NVMCON ; ; ; ; ; ; ; ; ; ; ; ;
; Set up NVMCON for block erase operation MOV #0x4042, W0 MOV W0, NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 MOV W0, TBLPAG MOV #tbloffset(PROG_ADDR), W0 TBLWTL W0, [W0] DISI #5 MOV MOV MOV MOV BSET NOP NOP #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR
Initialize PM Page Boundary SFR Initialize in-page EA[15:0] pointer Set base address of erase block Block all interrupts with priority <7 for next 5 instructions Write the 55 key Write the AA key Start the erase sequence Insert two NOPs after the erase command is asserted
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EXAMPLE 4-2: LOADING THE WRITE BUFFERS
; Set up NVMCON for row programming operations MOV #0x4001, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0, W2 ; MOV #HIGH_BYTE_0, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 1st_program_word MOV #LOW_WORD_1, W2 ; MOV #HIGH_BYTE_1, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 2nd_program_word MOV #LOW_WORD_2, W2 ; MOV #HIGH_BYTE_2, W3 ; ; Write PM low word into program latch TBLWTL W2, [W0] ; Write PM high byte into program latch TBLWTH W3, [W0++] * * * ; 63rd_program_word MOV #LOW_WORD_31, W2 ; MOV #HIGH_BYTE_31, W3 ; ; Write PM low word into program latch TBLWTL W2, [W0] ; Write PM high byte into program latch TBLWTH W3, [W0]
EXAMPLE 4-3:
DISI MOV MOV MOV MOV BSET BTSC BRA #5
INITIATING A PROGRAMMING SEQUENCE
; Block all interrupts with priority <7 ; for next 5 instructions ; ; ; ; ; ; Write the 55 key Write the AA key Start the erase sequence and wait for it to be completed #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR NVMCON, #15 $-2
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4.6.2 PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY
If a Flash location has been erased, it can be programmed using table write instructions to write an instruction word (24-bit) into the write latch. The TBLPAG register is loaded with the 8 Most Significant Bytes of the Flash address. The TBLWTL and TBLWTH instructions write the desired data into the write latches and specify the lower 16 bits of the program memory address to write to. To configure the NVMCON register for a word write, set the NVMOP bits (NVMCON<3:0>) to `0011'. The write is performed by executing the unlock sequence and setting the WR bit (see Example 4-4).
EXAMPLE 4-4:
PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY
; Setup a pointer to data Program Memory MOV #tblpage(PROG_ADDR), W0 ; MOV W0, TBLPAG ;Initialize PM Page Boundary SFR MOV #tbloffset(PROG_ADDR), W0 ;Initialize a register with program memory address MOV MOV TBLWTL TBLWTH #LOW_WORD_N, W2 #HIGH_BYTE_N, W3 W2, [W0] W3, [W0++] ; ; ; Write PM low word into program latch ; Write PM high byte into program latch
; Setup NVMCON for programming one word to data Program Memory MOV #0x4003, W0 ; MOV W0, NVMCON ; Set NVMOP bits to 0011 DISI MOV MOV MOV MOV BSET #5 #0x55, W0 W0, NVMKEY #0xAA, W0 W0, NVMKEY NVMCON, #WR ; Disable interrupts while the KEY sequence is written ; Write the key sequence
; Start the write cycle
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5.0
Note:
RESETS
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 7. Reset" (DS39712).
Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on POR and unchanged by all other Resets. Note: Refer to the specific peripheral or CPU section of this manual for register Reset states.
The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST. The following is a list of device Reset sources: * * * * * * * * * POR: Power-on Reset MCLR: Pin Reset SWR: RESET Instruction WDT: Watchdog Timer Reset BOR: Brown-out Reset CM: Configuration Mismatch Reset TRAPR: Trap Conflict Reset IOPUWR: Illegal Opcode Reset UWR: Uninitialized W Register Reset
All types of device Reset will set a corresponding status bit in the RCON register to indicate the type of Reset (see Register 5-1). A Power-on Reset will clear all bits, except for the BOR and POR bits (RCON<1:0>), which are set. The user may set or clear any bit at any time during code execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in software will not cause a device Reset to occur. The RCON register also has other bits associated with the Watchdog Timer and device power-saving states. The function of these bits is discussed in other sections of this manual. Note: The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful.
A simplified block diagram of the Reset module is shown in Figure 5-1.
FIGURE 5-1:
RESET SYSTEM BLOCK DIAGRAM
RESET Instruction Glitch Filter
MCLR WDT Module Sleep or Idle VDD Rise Detect VDD Brown-out Reset BOR POR SYSRST
Enable Voltage Regulator Trap Conflict Illegal Opcode Configuration Mismatch Uninitialized W Register
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REGISTER 5-1:
R/W-0 TRAPR bit 15 R/W-0 EXTR bit 7
RCON: RESET CONTROL REGISTER(1)
U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 CM R/W-0 VREGS bit 8 R/W-1 POR bit 0
R/W-0 IOPUWR
R/W-0 SWR
R/W-0 SWDTEN(2)
R/W-0 WDTO
R/W-0 SLEEP
R/W-0 IDLE
R/W-1 BOR
Legend: R = Readable bit -n = Value at POR bit 15
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 14
bit 13-10 bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit 1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an Address Pointer caused a Reset 0 = An illegal opcode or uninitialized W Reset has not occurred Unimplemented: Read as `0' CM: Configuration Word Mismatch Reset Flag bit 1 = A Configuration Word Mismatch Reset has occurred 0 = A Configuration Word Mismatch Reset has not occurred VREGS: Voltage Regulator Standby Enable bit 1 = Regulator remains active during Sleep 0 = Regulator goes to standby during Sleep EXTR: External Reset (MCLR) Pin bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred SWR: Software Reset (Instruction) Flag bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed SWDTEN: Software Enable/Disable of WDT bit(2) 1 = WDT is enabled 0 = WDT is disabled WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred SLEEP: Wake From Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode IDLE: Wake-up From Idle Flag bit 1 = Device has been in Idle mode 0 = Device has not been in Idle mode BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred. Note that BOR is also set after a Power-on Reset. 0 = A Brown-out Reset has not occurred POR: Power-on Reset Flag bit 1 = A Power-up Reset has occurred 0 = A Power-up Reset has not occurred All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. If the FWDTEN Configuration bit is `1' (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting.
Note 1: 2:
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TABLE 5-1: RESET FLAG BIT OPERATION
Setting Event Trap Conflict Event Illegal Opcode or Uninitialized W Register Access Configuration Mismatch Reset MCLR Reset RESET Instruction WDT Time-out PWRSAV #SLEEP Instruction PWRSAV #IDLE Instruction POR, BOR POR Clearing Event POR POR POR POR POR PWRSAV Instruction, POR POR POR -- -- Flag Bit TRAPR (RCON<15>) IOPUWR (RCON<14>) CM (RCON<9>) EXTR (RCON<7>) SWR (RCON<6>) WDTO (RCON<4>) SLEEP (RCON<3>) IDLE (RCON<2>) BOR (RCON<1>) POR (RCON<0>) Note:
All Reset flag bits may be set or cleared by the user software.
5.1
Clock Source Selection at Reset
5.2
Device Reset Times
If clock switching is enabled, the system clock source at device Reset is chosen as shown in Table 5-2. If clock switching is disabled, the system clock source is always selected according to the oscillator Configuration bits. Refer to Section 7.0 "Oscillator Configuration" for further details.
The Reset times for various types of device Reset are summarized in Table 5-3. Note that the system Reset signal, SYSRST, is released after the POR and PWRT delay times expire. The time at which the device actually begins to execute code will also depend on the system oscillator delays, which include the Oscillator Start-up Timer (OST) and the PLL lock time. The OST and PLL lock times occur in parallel with the applicable SYSRST delay times. The FSCM delay determines the time at which the FSCM begins to monitor the system clock source after the SYSRST signal is released.
TABLE 5-2:
OSCILLATOR SELECTION vs. TYPE OF RESET (CLOCK SWITCHING ENABLED)
Clock Source Determinant FNOSC Configuration bits (CW2<10:8>) COSC Control bits (OSCCON<14:12>)
Reset Type POR BOR MCLR WDTO SWR
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TABLE 5-3:
Reset Type POR
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
Clock Source SYSRST Delay System Clock Delay -- TLOCK TOST -- TLOCK TOST TOST + TLOCK -- -- -- -- -- -- FSCM Delay -- TFSCM TFSCM TFSCM -- TFSCM TFSCM TFSCM -- -- -- -- -- -- Notes 1, 2, 3 1, 2, 3, 5, 6 1, 2, 3, 4, 6 1, 2, 3, 4, 5, 6 2, 3 2, 3, 5, 6 2, 3, 4, 6 2, 3, 4, 5, 6 3 3 3 3 3 3
EC, FRC, FRCDIV, LPRC TPOR + TSTARTUP + TRST ECPLL, FRCPLL XT, HS, SOSC XTPLL, HSPLL TPOR + TSTARTUP + TRST TPOR + TSTARTUP + TRST TSTARTUP + TRST TSTARTUP + TRST TSTARTUP + TRST TSTARTUP + TRST TRST TRST TRST TRST TRST TRST
TPOR + TSTARTUP + TRST TOST + TLOCK
BOR
EC, FRC, FRCDIV, LPRC ECPLL, FRCPLL XT, HS, SOSC XTPLL, HSPLL
MCLR WDT Software Illegal Opcode Uninitialized W Trap Conflict Note 1: 2: 3: 4: 5: 6:
Any Clock Any Clock Any clock Any Clock Any Clock Any Clock
TPOR = Power-on Reset delay (10 s nominal). TSTARTUP = TVREG (10 s nominal) if on-chip regulator is enabled or TPWRT (64 ms nominal) if on-chip regulator is disabled. TRST = Internal state Reset time (32 s nominal). TOST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the oscillator clock to the system. TLOCK = PLL lock time. TFSCM = Fail-Safe Clock Monitor delay (100 s nominal).
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5.2.1 POR AND LONG OSCILLATOR START-UP TIMES 5.2.2.1 FSCM Delay for Crystal and PLL Clock Sources
The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low-frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released: * The oscillator circuit has not begun to oscillate. * The Oscillator Start-up Timer has not expired (if a crystal oscillator is used). * The PLL has not achieved a lock (if PLL is used). The device will not begin to execute code until a valid clock source has been released to the system. Therefore, the oscillator and PLL start-up delays must be considered when the Reset delay time must be known. When the system clock source is provided by a crystal oscillator and/or the PLL, a small delay, TFSCM, will automatically be inserted after the POR and PWRT delay times. The FSCM will not begin to monitor the system clock source until this delay expires. The FSCM delay time is nominally 100 s and provides additional time for the oscillator and/or PLL to stabilize. In most cases, the FSCM delay will prevent an oscillator failure trap at a device Reset when the PWRT is disabled.
5.3
Special Function Register Reset States
5.2.2
FAIL-SAFE CLOCK MONITOR (FSCM) AND DEVICE RESETS
Most of the Special Function Registers (SFRs) associated with the PIC24F CPU and peripherals are reset to a particular value at a device Reset. The SFRs are grouped by their peripheral or CPU function and their Reset values are specified in each section of this manual. The Reset value for each SFR does not depend on the type of Reset, with the exception of four registers. The Reset value for the Reset Control register, RCON, will depend on the type of device Reset. The Reset value for the Oscillator Control register, OSCCON, will depend on the type of Reset and the programmed values of the FNOSC bits in Flash Configuration Word 2 (CW2) (see Table 5-2). The RCFGCAL and NVMCON registers are only affected by a POR.
If the FSCM is enabled, it will begin to monitor the system clock source when SYSRST is released. If a valid clock source is not available at this time, the device will automatically switch to the FRC oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine.
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NOTES:
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6.0
Note:
INTERRUPT CONTROLLER
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 8. Interrupts" (DS39707).
6.1.1
ALTERNATE INTERRUPT VECTOR TABLE
The PIC24F interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the PIC24F CPU. It has the following features: Up to 8 processor exceptions and software traps 7 user-selectable priority levels Interrupt Vector Table (IVT) with up to 118 vectors A unique vector for each interrupt or exception source * Fixed priority within a specified user priority level * Alternate Interrupt Vector Table (AIVT) for debug support * Fixed interrupt entry and return latencies * * * *
The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 6-1. Access to the AIVT is provided by the ALTIVT control bit (INTCON2<15>). If the ALTIVT bit is set, all interrupt and exception processes will use the alternate vectors instead of the default vectors. The alternate vectors are organized in the same manner as the default vectors. The AIVT supports emulation and debugging efforts by providing a means to switch between an application and a support environment without requiring the interrupt vectors to be reprogrammed. This feature also enables switching between applications for evaluation of different software algorithms at run time. If the AIVT is not needed, the AIVT should be programmed with the same addresses used in the IVT.
6.2
Reset Sequence
6.1
Interrupt Vector Table
The Interrupt Vector Table (IVT) is shown in Figure 6-1. The IVT resides in program memory, starting at location 000004h. The IVT contains 126 vectors, consisting of 8 non-maskable trap vectors, plus up to 118 sources of interrupt. In general, each interrupt source has its own vector. Each interrupt vector contains a 24-bit wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR). Interrupt vectors are prioritized in terms of their natural priority; this is linked to their position in the vector table. All other things being equal, lower addresses have a higher natural priority. For example, the interrupt associated with vector 0 will take priority over interrupts at any other vector address. PIC24FJ256GB110 family devices implement non-maskable traps and unique interrupts. These are summarized in Table 6-1 and Table 6-2.
A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The PIC24F devices clear their registers in response to a Reset which forces the PC to zero. The microcontroller then begins program execution at location 000000h. The user programs a GOTO instruction at the Reset address, which redirects program execution to the appropriate start-up routine. Note: Any unimplemented or unused vector locations in the IVT and AIVT should be programmed with the address of a default interrupt handler routine that contains a RESET instruction.
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FIGURE 6-1: PIC24F INTERRUPT VECTOR TABLE
Reset - GOTO Instruction Reset - GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 -- -- -- Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 -- -- -- Interrupt Vector 116 Interrupt Vector 117 Reserved Reserved Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 -- -- -- Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 -- -- -- Interrupt Vector 116 Interrupt Vector 117 Start of Code 000000h 000002h 000004h
000014h
Decreasing Natural Order Priority
00007Ch 00007Eh 000080h
Interrupt Vector Table (IVT)(1)
0000FCh 0000FEh 000100h 000102h
000114h
Alternate Interrupt Vector Table (AIVT)(1) 00017Ch 00017Eh 000180h
0001FEh 000200h
Note 1:
See Table 6-2 for the interrupt vector list.
TABLE 6-1:
0 1 2 3 4 5 6 7
TRAP VECTOR DETAILS
IVT Address 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h AIVT Address 000104h 000106h 000108h 00010Ah 00010Ch 00010Eh 000110h 0001172h Reserved Oscillator Failure Address Error Stack Error Math Error Reserved Reserved Reserved
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Vector Number
Trap Source
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TABLE 6-2: IMPLEMENTED INTERRUPT VECTORS
Vector Number 13 18 67 77 0 20 29 53 54 17 16 50 49 85 84 1 5 37 38 39 40 22 23 93 19 72 2 6 25 26 41 42 43 44 92 45 62 9 10 32 33 90 91 IVT Address 00002Eh 000038h 00009Ah 0000AEh 000014h 00003Ch 00004Eh 00007Eh 000080h 000036h 000034h 000078h 000076h 0000BEh 0000BCh 000016h 00001Eh 00005Eh 000060h 000062h 000064h 000040h 000042h 0000CEh 00003Ah 0000A4h 000018h 000020h 000046h 000048h 000066h 000068h 00006Ah 00006Ch 0000CCh 00006Eh 000090h 000026h 000028h 000054h 000056h 0000C8h 0000CAh AIVT Address 00012Eh 000138h 00019Ah 0001AEh 000114h 00013Ch 00014Eh 00017Eh 000180h 000136h 000134h 000178h 000176h 0001BEh 0001BCh 000116h 00011Eh 00015Eh 000160h 000162h 000164h 000140h 000142h 0001CEh 00013Ah 0001A4h 000118h 000120h 000146h 000148h 000166h 000168h 00016Ah 00016Ch 0001CCh 00016Eh 000190h 000126h 000128h 000154h 000156h 0001C8h 0001CAh Interrupt Bit Locations Flag IFS0<13> IFS1<2> IFS4<3> IFS4<13> IFS0<0> IFS1<4> IFS1<13> IFS3<5> IFS3<6> IFS1<1> IFS1<0> IFS3<2> IFS3<1> IFS5<5> IFS5<4> IFS0<1> IFS0<5> IFS2<5> IFS2<6> IFS2<7> IFS2<8> IFS1<6> IFS1<7> IFS5<13> IFS1<3> IFS4<8> IFS0<2> IFS0<6> IFS1<9> IFS1<10> IFS2<9> IFS2<10> IFS2<11> IFS2<12> IFS5<12> IFS2<13> IFS3<14> IFS0<9> IFS0<10> IFS2<0> IFS2<1> IFS5<10> IFS5<11> Enable IEC0<13> IEC1<2> IEC4<3> IEC4<13> IEC0<0> IEC1<4> IEC1<13> IEC3<5> IEC3<6> IEC1<1> IEC1<0> IEC3<2> IEC3<1> IEC5<5> IEC5<4> IEC0<1> IEC0<5> IEC2<5> IEC2<6> IEC2<7> IEC2<8> IEC1<6> IEC1<7> IEC5<13> IEC1<3> IEC4<8> IEC0<2> IEC0<6> IEC1<9> IEC1<10> IEC2<9> IEC2<10> IEC2<11> IEC2<12> IEC5<12> IEC2<13> IEC3<14> IEC0<9> IEC0<10> IEC2<0> IEC2<1> IEC5<10> IEC5<11> Priority IPC3<6:4> IPC4<10:8> IPC16<14:12> IPC19<6:4> IPC0<2:0> IPC5<2:0> IPC7<6:4> IPC13<6:4> IPC13<10:8> IPC4<6:4> IPC4<2:0> IPC12<10:8> IPC12<6:4> IPC21<6:4> IPC21<2:0> IPC0<6:4> IPC1<6:4> IPC9<6:4> IPC9<10:8> IPC9<14:12> IPC10<2:0> IPC5<10:8> IPC5<14:12> IPC23<6:4> IPC4<14:12> IPC18<2:0> IPC0<10:8> IPC1<10:8> IPC6<6:4> IPC6<10:8> IPC10<6:4> IPC10<10:8> IPC10<14:12> IPC11<2:0> IPC23<2:0> IPC11<6:4> IPC15<10:8> IPC2<6:4> IPC2<10:8> IPC8<2:0> IPC8<6:4> IPC22<10:8> IPC22<14:12> Interrupt Source ADC1 Conversion Done Comparator Event CRC Generator CTMU Event External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 I2C1 Master Event I2C1 Slave Event I2C2 Master Event I2C2 Slave Event I2C3 Master Event I2C3 Slave Event Input Capture 1 Input Capture 2 Input Capture 3 Input Capture 4 Input Capture 5 Input Capture 6 Input Capture 7 Input Capture 8 Input Capture 9 Input Change Notification LVD Low-Voltage Detect Output Compare 1 Output Compare 2 Output Compare 3 Output Compare 4 Output Compare 5 Output Compare 6 Output Compare 7 Output Compare 8 Output Compare 9 Parallel Master Port Real-Time Clock/Calendar SPI1 Error SPI1 Event SPI2 Error SPI2 Event SPI3 Error SPI3 Event
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TABLE 6-2: IMPLEMENTED INTERRUPT VECTORS (CONTINUED)
Vector Number 3 7 8 27 28 65 11 12 66 30 31 81 82 83 87 88 89 86 IVT Address 00001Ah 000022h 000024h 00004Ah 00004Ch 000096h 00002Ah 00002Ch 000098h 000050h 000052h 0000B6h 0000B8h 0000BAh 0000C2h 0000C4h 0000C6h 0000C0h AIVT Address 00011Ah 000122h 000124h 00014Ah 00014Ch 000196h 00012Ah 00012Ch 000198h 000150h 000152h 0001B6h 0001B8h 0001BAh 0001C2h 0001C4h 0001C6h 0001C0h Interrupt Bit Locations Flag IFS0<3> IFS0<7> IFS0<8> IFS1<11> IFS1<12> IFS4<1> IFS0<11> IFS0<12> IFS4<2> IFS1<14> IFS1<15> IFS5<1> IFS5<2> IFS5<3> IFS5<7> IFS5<8> IFS5<9> IFS5<6> Enable IEC0<3> IEC0<7> IEC0<8> IEC1<11> IEC1<12> IEC4<1> IEC0<11> IEC0<12> IEC4<2> IEC1<14> IEC1<15> IEC5<1> IEC5<2> IEC5<3> IEC5<7> IEC5<8> IEC5<9> IEC5<6> Priority IPC0<14:12> IPC1<14:12> IPC2<2:0> IPC6<14:12> IPC7<2:0> IPC16<6:4> IPC2<14:12> IPC3<2:0> IPC16<10:8> IPC7<10:8> IPC7<14:12> IPC20<6:4> IPC20<10:8> IPC20<14:12> IPC21<14:12> IPC22<2:0> IPC22<6:4> IPC21<10:8> Interrupt Source Timer1 Timer2 Timer3 Timer4 Timer5 UART1 Error UART1 Receiver UART1 Transmitter UART2 Error UART2 Receiver UART2 Transmitter UART3 Error UART3 Receiver UART3 Transmitter UART4 Error UART4 Receiver UART4 Transmitter USB Interrupt
6.3
Interrupt Control and Status Registers
The PIC24FJ256GB110 family of devices implements a total of 36 registers for the interrupt controller: * * * * * INTCON1 INTCON2 IFS0 through IFS5 IEC0 through IEC5 IPC0 through IPC23 (except IPC14 and IPC17)
The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the order of their vector numbers, as shown in Table 6-2. For example, the INT0 (External Interrupt 0) is shown as having a vector number and a natural order priority of 0. Thus, the INT0IF status bit is found in IFS0<0>, the INT0IE enable bit in IEC0<0> and the INT0IP<2:0> priority bits in the first position of IPC0 (IPC0<2:0>). Although they are not specifically part of the interrupt control hardware, two of the CPU control registers contain bits that control interrupt functionality. The ALU STATUS register (SR) contains the IPL2:IPL0 bits (SR<7:5>). These indicate the current CPU interrupt priority level. The user may change the current CPU priority level by writing to the IPL bits. The CORCON register contains the IPL3 bit, which, together with IPL2:IPL0, indicates the current CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user software. All interrupt registers are described in Register 6-1 through Register 6-38, in the following pages.
Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit, as well as the control and status flags for the processor trap sources. The INTCON2 register controls the external interrupt request signal behavior and the use of the Alternate Interrupt Vector Table. The IFSx registers maintain all of the interrupt request flags. Each source of interrupt has a status bit which is set by the respective peripherals, or an external signal, and is cleared via software. The IECx registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. The IPCx registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels.
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Preliminary
(c) 2008 Microchip Technology Inc.
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REGISTER 6-1:
U-0 -- bit 15 R/W-0 IPL2 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
(2,3)
SR: ALU STATUS REGISTER (IN CPU)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R-0 DC(1) bit 8 R/W-0 IPL1(2,3) R/W-0 IPL0(2,3) R-0 RA(1) R/W-0 N(1) R/W-0 OV(1) R/W-0 Z(1) R/W-0 C(1) bit 0
IPL2:IPL0: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU interrupt priority level is 7 (15). User interrupts disabled. 110 = CPU interrupt priority level is 6 (14) 101 = CPU interrupt priority level is 5 (13) 100 = CPU interrupt priority level is 4 (12) 011 = CPU interrupt priority level is 3 (11) 010 = CPU interrupt priority level is 2 (10) 001 = CPU interrupt priority level is 1 (9) 000 = CPU interrupt priority level is 0 (8) See Register 2-1 for the description of the remaining bit(s) that are not dedicated to interrupt control functions. The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU interrupt priority level. The value in parentheses indicates the interrupt priority level if IPL3 = 1. The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
Note 1: 2: 3:
REGISTER 6-2:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 3
CORCON: CPU CONTROL REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- U-0 -- U-0 -- R/C-0 IPL3(2) R/W-0 PSV(1) U-0 -- U-0 -- bit 0 C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
IPL3: CPU Interrupt Priority Level Status bit(2) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less See Register 2-2 for the description of the remaining bit(s) that are not dedicated to interrupt control functions. The IPL3 bit is concatenated with the IPL2:IPL0 bits (SR<7:5>) to form the CPU interrupt priority level.
Note 1: 2:
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Preliminary
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REGISTER 6-3:
R/W-0 NSTDIS bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 MATHERR R/W-0 ADDRERR R/W-0 STKERR R/W-0 OSCFAIL U-0 -- bit 0
INTCON1: INTERRUPT CONTROL REGISTER 1
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8
NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled Unimplemented: Read as `0' MATHERR: Arithmetic Error Trap Status bit 1 = Overflow trap has occurred 0 = Overflow trap has not occurred ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred Unimplemented: Read as `0'
bit 14-5 bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 6-4:
R/W-0 ALTIVT bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 INT2EP R/W-0 INT1EP
INTCON2: INTERRUPT CONTROL REGISTER 2
R-0 DISI U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 INT0EP bit 0
ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use Alternate Interrupt Vector Table 0 = Use standard (default) vector table DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active Unimplemented: Read as `0' INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge
bit 14
bit 13-3 bit 2
bit 1
bit 0
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Preliminary
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REGISTER 6-5:
U-0 -- bit 15 R/W-0 T2IF bit 7
IFS0: INTERRUPT FLAG STATUS REGISTER 0
U-0 -- R/W-0 AD1IF R/W-0 U1TXIF R/W-0 U1RXIF R/W-0 SPI1IF R/W-0 SPF1IF R/W-0 T3IF bit 8 R/W-0 INT0IF bit 0
R/W-0 OC2IF
R/W-0 IC2IF
U-0 --
R/W-0 T1IF
R/W-0 OC1IF
R/W-0 IC1IF
Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4 bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as `0' AD1IF: A/D Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1TXIF: UART1 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1RXIF: UART1 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPI1IF: SPI1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPF1IF: SPI1 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T3IF: Timer3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T2IF: Timer2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC2IF: Output Compare Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC2IF: Input Capture Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred
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REGISTER 6-6:
R/W-0 U2TXIF bit 15 R/W-0 IC8IF bit 7
IFS1: INTERRUPT FLAG STATUS REGISTER 1
R/W-0 U2RXIF R/W-0 INT2IF R/W-0 T5IF R/W-0 T4IF R/W-0 OC4IF R/W-0 OC3IF U-0 -- bit 8 R/W-0 IC7IF U-0 -- R/W-0 INT1IF R/W-0 CNIF R/W-0 CMIF R/W-0 MI2C1IF R/W-0 SI2C1IF bit 0
Legend: R = Readable bit -n = Value at POR bit 15
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8 bit 7
bit 6
bit 5 bit 4
bit 3
bit 2
bit 1
bit 0
U2TXIF: UART2 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U2RXIF: UART2 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T5IF: Timer5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T4IF: Timer4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC4IF: Output Compare Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC3IF: Output Compare Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' IC8IF: Input Capture Channel 8 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC7IF: Input Capture Channel 7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred CMIF: Comparator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred MI2C1IF: Master I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred
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Preliminary
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REGISTER 6-7:
U-0 -- bit 15 R/W-0 IC5IF bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 IC4IF R/W-0 IC3IF U-0 -- U-0 -- U-0 -- R/W-0 SPI2IF
IFS2: INTERRUPT FLAG STATUS REGISTER 2
U-0 -- R/W-0 PMPIF R/W-0 OC8IF R/W-0 OC7IF R/W-0 OC6IF R/W-0 OC5IF R/W-0 IC6IF bit 8 R/W-0 SPF2IF bit 0
Unimplemented: Read as `0' PMPIF: Parallel Master Port Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC8IF: Output Compare Channel 8 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC7IF: Output Compare Channel 7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC6IF: Output Compare Channel 6 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC5IF: Output Compare Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC6IF: Input Capture Channel 6 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC5IF: Input Capture Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC4IF: Input Capture Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC3IF: Input Capture Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPF2IF: SPI2 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4-2 bit 1
bit 0
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REGISTER 6-8:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 INT4IF R/W-0 INT3IF U-0 -- U-0 -- R/W-0 MI2C2IF R/W-0 SI2C2IF U-0 -- bit 0
IFS3: INTERRUPT FLAG STATUS REGISTER 3
R/W-0 RTCIF U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8
Unimplemented: Read as `0' RTCIF: Real-Time Clock/Calendar Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' INT4IF: External Interrupt 4 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT3IF: External Interrupt 3 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' MI2C2IF: Master I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0'
bit 13-7 bit 6
bit 5
bit 4-3 bit 2
bit 1
bit 0
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Preliminary
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REGISTER 6-9:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- R/W-0 CRCIF R/W-0 U2ERIF R/W-0 U1ERIF U-0 -- bit 0
IFS4: INTERRUPT FLAG STATUS REGISTER 4
U-0 -- R/W-0 CTMUIF U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 LVDIF bit 8
Unimplemented: Read as `0' CTMUIF: CTMU Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' LVDIF: Low-Voltage Detect Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' CRCIF: CRC Generator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U2ERIF: UART2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1ERIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0'
bit 12-9 bit 8
bit 7-4 bit 3
bit 2
bit 1
bit 0
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REGISTER 6-10:
U-0 -- bit 15 R/W-0 U4ERIF bit 7
IFS5: INTERRUPT FLAG STATUS REGISTER 5
U-0 -- R/W-0 IC9IF R/W-0 OC9IF R/W-0 SPI3IF R/W-0 SPF3IF R/W-0 U4TXIF R/W-0 U4RXIF bit 8 U-0 -- bit 0
R/W-0 USB1IF
R/W-0 MI2C3IF
R/W-0 SI2C3IF
R/W-0 U3TXIF
R/W-0 U3RXIF
R/W-0 U3ERIF
Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as `0' IC9IF: Input Capture Channel 9 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC9IF: Output Compare Channel 9 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPI3IF: SPI3 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPF3IF: SPI3 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U4TXIF: UART4 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U4RXIF: UART4 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U4ERIF: UART4 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred USB1IF: USB1 (USB OTG) Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred MI2C3IF: Master I2C3 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SI2C3IF: Slave I2C3 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U3TXIF: UART3 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U3RXIF: UART3 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U3ERIF: UART3 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0'
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Preliminary
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REGISTER 6-11:
U-0 -- bit 15 R/W-0 T2IE bit 7
IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
U-0 -- R/W-0 AD1IE R/W-0 U1TXIE R/W-0 U1RXIE R/W-0 SPI1IE R/W-0 SPF1IE R/W-0 T3IE bit 8 R/W-0 INT0IE bit 0
R/W-0 OC2IE
R/W-0 IC2IE
U-0 --
R/W-0 T1IE
R/W-0 OC1IE
R/W-0 IC1IE
Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4 bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as `0' AD1IE: A/D Conversion Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U1TXIE: UART1 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U1RXIE: UART1 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPI1IE: SPI1 Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPF1IE: SPI1 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T3IE: Timer3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T2IE: Timer2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC2IE: Output Compare Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC2IE: Input Capture Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled
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REGISTER 6-12:
R/W-0 U2TXIE bit 15 R/W-0 IC8IE bit 7
IEC1: INTERRUPT ENABLE CONTROL REGISTER 1
R/W-0 INT2IE(1) R/W-0 T5IE R/W-0 T4IE R/W-0 OC4IE R/W-0 OC3IE U-0 -- bit 8
R/W-0 U2RXIE
R/W-0 IC7IE
U-0 --
R/W-0 INT1IE(1)
R/W-0 CNIE
R/W-0 CMIE
R/W-0 MI2C1IE
R/W-0 SI2C1IE bit 0
Legend: R = Readable bit -n = Value at POR bit 15
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8 bit 7
bit 6
bit 5 bit 4
bit 3
bit 2
U2TXIE: UART2 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U2RXIE: UART2 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled INT2IE: External Interrupt 2 Enable bit(1) 1 = Interrupt request enabled 0 = Interrupt request not enabled T5IE: Timer5 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T4IE: Timer4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC4IE: Output Compare Channel 4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC3IE: Output Compare Channel 3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' IC8IE: Input Capture Channel 8 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC7IE: Input Capture Channel 7 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' INT1IE: External Interrupt 1 Enable bit(1) 1 = Interrupt request enabled 0 = Interrupt request not enabled CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled CMIE: Comparator Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled If an external interrupt is enabled, the interrupt input must also be configured to an available RPx or PRIx pin. See Section 9.4 "Peripheral Pin Select" for more information.
Note 1:
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REGISTER 6-12:
bit 1
IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED)
bit 0
MI2C1IE: Master I2C1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SI2C1IE: Slave I2C1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled If an external interrupt is enabled, the interrupt input must also be configured to an available RPx or PRIx pin. See Section 9.4 "Peripheral Pin Select" for more information.
Note 1:
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REGISTER 6-13:
U-0 -- bit 15 R/W-0 IC5IE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 IC4IE R/W-0 IC3IE U-0 -- U-0 -- U-0 -- R/W-0 SPI2IE
IEC2: INTERRUPT ENABLE CONTROL REGISTER 2
U-0 -- R/W-0 PMPIE R/W-0 OC8IE R/W-0 OC7IE R/W-0 OC6IE R/W-0 OC5IE R/W-0 IC6IE bit 8 R/W-0 SPF2IE bit 0
Unimplemented: Read as `0' PMPIE: Parallel Master Port Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC8IE: Output Compare Channel 8 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC7IE: Output Compare Channel 7 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC6IE: Output Compare Channel 6 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC5IE: Output Compare Channel 5 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC6IE: Input Capture Channel 6 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC5IE: Input Capture Channel 5 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC4IE: Input Capture Channel 4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC3IE: Input Capture Channel 3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4-2 bit 1
bit 0
(c) 2008 Microchip Technology Inc.
Preliminary
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REGISTER 6-14:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 INT4IE
(1)
IEC3: INTERRUPT ENABLE CONTROL REGISTER 3
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 INT3IE
(1)
R/W-0 RTCIE
U-0 --
U-0 --
R/W-0 MI2C2IE
R/W-0 SI2C2IE
U-0 -- bit 0
Unimplemented: Read as `0' RTCIE: Real-Time Clock/Calendar Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' INT4IE: External Interrupt 4 Enable bit(1) 1 = Interrupt request enabled 0 = Interrupt request not enabled INT3IE: External Interrupt 3 Enable bit(1) 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' MI2C2IE: Master I2C2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SI2C2IE: Slave I2C2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' If an external interrupt is enabled, the interrupt input must also be configured to an available RPx or PRIx pin. See Section 9.4 "Peripheral Pin Select" for more information.
bit 13-7 bit 6
bit 5
bit 4-3 bit 2
bit 1
bit 0 Note 1:
DS39897B-page 84
Preliminary
(c) 2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
REGISTER 6-15:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- R/W-0 CRCIE R/W-0 U2ERIE R/W-0 U1ERIE U-0 -- bit 0
IEC4: INTERRUPT ENABLE CONTROL REGISTER 4
U-0 -- R/W-0 CTMUIE U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 LVDIE bit 8
Unimplemented: Read as `0' CTMUIE: CTMU Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' LVDIE: Low-Voltage Detect Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' CRCIE: CRC Generator Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U2ERIE: UART2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0'
bit 12-9 bit 8
bit 7-4 bit 3
bit 2
bit 1
bit 0
(c) 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 85
PIC24FJ256GB110 FAMILY
REGISTER 6-16:
U-0 -- bit 15 R/W-0 U4ERIE bit 7
IEC5: INTERRUPT ENABLE CONTROL REGISTER 5
U-0 -- R/W-0 IC9IE R/W-0 OC9IE R/W-0 SPI3IE R/W-0 SPF3IE R/W-0 U4TXIE R/W-0 U4RXIE bit 8 U-0 -- bit 0
R/W-0 USB1IE
R/W-0 MI2C3IE
R/W-0 SI2C3IE
R/W-0 U3TXIE
R/W-0 U3RXIE
R/W-0 U3ERIE
Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as `0' IC9IE: Input Capture Channel 9 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC9IE: Output Compare Channel 9 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPI3IE: SPI3 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPF3IE: SPI3 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U4TXIE: UART4 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U4RXIE: UART4 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U4ERIE: UART4 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled USB1IE: USB1 (USB OTG) Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled MI2C3IE: Master I2C3 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SI2C3IE: Slave I2C3 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U3TXIE: UART3 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U3RXIE: UART3 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U3ERIE: UART3 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0'
DS39897B-page 86
Preliminary
(c) 2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
REGISTER 6-17:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 IC1IP2 R/W-0 IC1IP1 R/W-0 IC1IP0 U-0 -- R/W-1 INT0IP2 R/W-0 INT0IP1
IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0
R/W-0 T1IP1 R/W-0 T1IP0 U-0 -- R/W-1 OC1IP2 R/W-0 OC1IP1 R/W-0 OC1IP0 bit 8 R/W-0 INT0IP0 bit 0
R/W-1 T1IP2
Unimplemented: Read as `0' T1IP2:T1IP0: Timer1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' OC1IP2:OC1IP0: Output Compare Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' IC1IP2:IC1IP0: Input Capture Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' INT0IP2:INT0IP0: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled
bit 11 bit 10-8
bit 7 bit 6-4
bit 3 bit 2-0
(c) 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 87
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REGISTER 6-18:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 IC2IP2 R/W-0 IC2IP1 R/W-0 IC2IP0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1
R/W-0 T2IP1 R/W-0 T2IP0 U-0 -- R/W-1 OC2IP2 R/W-0 OC2IP1 R/W-0 OC2IP0 bit 8
R/W-1 T2IP2
Unimplemented: Read as `0' T2IP2:T2IP0: Timer2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' OC2IP2:OC2IP0: Output Compare Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' IC2IP2:IC2IP0: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0'
bit 11 bit 10-8
bit 7 bit 6-4
bit 3-0
DS39897B-page 88
Preliminary
(c) 2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
REGISTER 6-19:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 SPF1IP2 R/W-0 SPF1IP1 R/W-0 SPF1IP0 U-0 -- R/W-1 T3IP2 R/W-0 T3IP1
IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2
R/W-0 U1RXIP1 R/W-0 U1RXIP0 U-0 -- R/W-1 SPI1IP2 R/W-0 SPI1IP1 R/W-0 SPI1IP0 bit 8 R/W-0 T3IP0 bit 0
R/W-1 U1RXIP2
Unimplemented: Read as `0' U1RXIP2:U1RXIP0: UART1 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SPI1IP2:SPI1IP0: SPI1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SPF1IP2:SPF1IP0: SPI1 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' T3IP2:T3IP0: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled
bit 11 bit 10-8
bit 7 bit 6-4
bit 3 bit 2-0
(c) 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 89
PIC24FJ256GB110 FAMILY
REGISTER 6-20:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 AD1IP2 R/W-0 AD1IP1 R/W-0 AD1IP0 U-0 -- R/W-1 U1TXIP2 R/W-0 U1TXIP1
IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 U1TXIP0 bit 0
Unimplemented: Read as `0' AD1IP2:AD1IP0: A/D Conversion Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' U1TXIP2:U1TXIP0: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled
bit 3 bit 2-0
DS39897B-page 90
Preliminary
(c) 2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
REGISTER 6-21:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 MI2C1P2 R/W-0 MI2C1P1 R/W-0 MI2C1P0 U-0 -- R/W-1 SI2C1P2 R/W-0 SI2C1P1
IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4
R/W-0 CNIP1 R/W-0 CNIP0 U-0 -- R/W-1 CMIP2 R/W-0 CMIP1 R/W-0 CMIP0 bit 8 R/W-0 SI2C1P0 bit 0
R/W-1 CNIP2
Unimplemented: Read as `0' CNIP2:CNIP0: Input Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' CMIP2:CMIP0: Comparator Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' MI2C1P2:MI2C1P0: Master I2C1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SI2C1P2:SI2C1P0: Slave I2C1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled
bit 11 bit 10-8
bit 7 bit 6-4
bit 3 bit 2-0
(c) 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 91
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REGISTER 6-22:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 INT1IP2 R/W-0 INT1IP1
IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5
R/W-0 IC8IP1 R/W-0 IC8IP0 U-0 -- R/W-1 IC7IP2 R/W-0 IC7IP1 R/W-0 IC7IP0 bit 8 R/W-0 INT1IP0 bit 0
R/W-1 IC8IP2
Unimplemented: Read as `0' IC8IP2:IC8IP0: Input Capture Channel 8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' IC7IP2:IC7IP0: Input Capture Channel 7 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' INT1IP2:INT1IP0: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled
bit 11 bit 10-8
bit 7-3 bit 2-0
DS39897B-page 92
Preliminary
(c) 2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
REGISTER 6-23:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 OC3IP2 R/W-0 OC3IP1 R/W-0 OC3IP0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6
R/W-0 T4IP1 R/W-0 T4IP0 U-0 -- R/W-1 OC4IP2 R/W-0 OC4IP1 R/W-0 OC4IP0 bit 8
R/W-1 T4IP2
Unimplemented: Read as `0' T4IP2:T4IP0: Timer4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' OC4IP2:OC4IP0: Output Compare Channel 4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' OC3IP2:OC3IP0: Output Compare Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0'
bit 11 bit 10-8
bit 7 bit 6-4
bit 3-0
(c) 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 93
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REGISTER 6-24:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 INT2IP2 R/W-0 INT2IP1 R/W-0 INT2IP0 U-0 -- R/W-1 T5IP2 R/W-0 T5IP1
IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7
R/W-0 U2TXIP1 R/W-0 U2TXIP0 U-0 -- R/W-1 U2RXIP2 R/W-0 U2RXIP1 R/W-0 U2RXIP0 bit 8 R/W-0 T5IP0 bit 0
R/W-1 U2TXIP2
Unimplemented: Read as `0' U2TXIP2:U2TXIP0: UART2 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' U2RXIP2:U2RXIP0: UART2 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' INT2IP2:INT2IP0: External Interrupt 2 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' T5IP2:T5IP0: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled
bit 11 bit 10-8
bit 7 bit 6-4
bit 3 bit 2-0
DS39897B-page 94
Preliminary
(c) 2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
REGISTER 6-25:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 SPI2IP2 R/W-0 SPI2IP1 R/W-0 SPI2IP0 U-0 -- R/W-1 SPF2IP2 R/W-0 SPF2IP1
IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 SPF2IP0 bit 0
Unimplemented: Read as `0' SPI2IP2:SPI2IP0: SPI2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SPF2IP2:SPF2IP0: SPI2 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled
bit 3 bit 2-0
(c) 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 95
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REGISTER 6-26:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 IC3IP2 R/W-0 IC3IP1 R/W-0 IC3IP0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9
R/W-0 IC5IP1 R/W-0 IC5IP0 U-0 -- R/W-1 IC4IP2 R/W-0 IC4IP1 R/W-0 IC4IP0 bit 8
R/W-1 IC5IP2
Unimplemented: Read as `0' IC5IP2:IC5IP0: Input Capture Channel 5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' IC4IP2:IC4IP0: Input Capture Channel 4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' IC3IP2:IC3IP0: Input Capture Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0'
bit 11 bit 10-8
bit 7 bit 6-4
bit 3-0
DS39897B-page 96
Preliminary
(c) 2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
REGISTER 6-27:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 OC5IP2 R/W-0 OC5IP1 R/W-0 OC5IP0 U-0 -- R/W-1 IC6IP2 R/W-0 IC6IP1
IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10
R/W-0 OC7IP1 R/W-0 OC7IP0 U-0 -- R/W-1 OC6IP2 R/W-0 OC6IP1 R/W-0 OC6IP0 bit 8 R/W-0 IC6IP0 bit 0
R/W-1 OC7IP2
Unimplemented: Read as `0' OC7IP2:OC7IP0: Output Compare Channel 7 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' OC6IP2:OC6IP0: Output Compare Channel 6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' OC5IP2:OC5IP0: Output Compare Channel 5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' IC6IP2:IC6IP0: Input Capture Channel 6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled
bit 11 bit 10-8
bit 7 bit 6-4
bit 3 bit 2-0
(c) 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 97
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REGISTER 6-28:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 PMPIP2 R/W-0 PMPIP1 R/W-0 PMPIP0 U-0 -- R/W-1 OC8IP2 R/W-0 OC8IP1
IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 OC8IP0 bit 0
Unimplemented: Read as `0' PMPIP2:PMPIP0: Parallel Master Port Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' OC8IP2:OC8IP0: Output Compare Channel 8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled
bit 3 bit 2-0
DS39897B-page 98
Preliminary
(c) 2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
REGISTER 6-29:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 SI2C2P2 R/W-0 SI2C2P1 R/W-0 SI2C2P0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12
U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 MI2C2P2 R/W-0 MI2C2P1 R/W-0 MI2C2P0 bit 8
Unimplemented: Read as `0' MI2C2P2:MI2C2P0: Master I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SI2C2P2:SI2C2P0: Slave I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0'
bit 7 bit 6-4
bit 3-0
(c) 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 99
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REGISTER 6-30:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 INT3IP2 R/W-0 INT3IP1 R/W-0 INT3IP0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13
U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 INT4IP2 R/W-0 INT4IP1 R/W-0 INT4IP0 bit 8
Unimplemented: Read as `0' INT4IP2:INT4IP0: External Interrupt 4 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' INT3IP2:INT3IP0: External Interrupt 3 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0'
bit 7 bit 6-4
bit 3-0
DS39897B-page 100
Preliminary
(c) 2008 Microchip Technology Inc.
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REGISTER 6-31:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15
U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 RTCIP2 R/W-0 RTCIP1 R/W-0 RTCIP0 bit 8
Unimplemented: Read as `0' RTCIP2:RTCIP0: Real-Time Clock/Calendar Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0'
bit 7-0
(c) 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 101
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REGISTER 6-32:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 U1ERIP2 R/W-0 U1ERIP1 R/W-0 U1ERIP0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16
R/W-0 CRCIP1 R/W-0 CRCIP0 U-0 -- R/W-1 U2ERIP2 R/W-0 U2ERIP1 R/W-0 U2ERIP0 bit 8
R/W-1 CRCIP2
Unimplemented: Read as `0' CRCIP2:CRCIP0: CRC Generator Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' U2ERIP2:U2ERIP0: UART2 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' U1ERIP2:U1ERIP0: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0'
bit 11 bit 10-8
bit 7 bit 6-4
bit 3-0
DS39897B-page 102
Preliminary
(c) 2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
REGISTER 6-33:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-3 bit 2-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 LVDIP2 R/W-0 LVDIP1
IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 LVDIP0 bit 0
Unimplemented: Read as `0' LVDIP2:LVDIP0: Low-Voltage Detect Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled
REGISTER 6-34:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4
IPC19: INTERRUPT PRIORITY CONTROL REGISTER 19
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8
R/W-1 CTMUIP2
R/W-0 CTMUIP1
R/W-0 CTMUIP0
U-0 --
U-0 --
U-0 --
U-0 -- bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' CTMUIP2:CTMUIP0: CTMU Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0'
bit 3-0
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REGISTER 6-35:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 U3ERIP2 R/W-0 U3ERIP1 R/W-0 U3ERIP0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20
R/W-0 U3TXIP1 R/W-0 U3TXIP0 U-0 -- R/W-1 U3RXIP2 R/W-0 U3RXIP1 R/W-0 U3RXIP0 bit 8
R/W-1 U3TXIP2
Unimplemented: Read as `0' U3TXIP2:U3TXIP0: UART3 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' U3RXIP2:U3RXIP0: UART3 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' U3ERIP2:U3ERIP0: UART3 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0'
bit 11 bit 10-8
bit 7 bit 6-4
bit 3-0
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REGISTER 6-36:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 MI2C3P2 R/W-0 MI2C3P1 R/W-0 MI2C3P0 U-0 -- R/W-1 SI2C3P2 R/W-0 SI2C3P1
IPC21: INTERRUPT PRIORITY CONTROL REGISTER 21
R/W-0 U4ERIP1 R/W-0 U4ERIP0 U-0 -- R/W-1 USB1IP2 R/W-0 USB1IP1 R/W-0 USB1IP0 bit 8 R/W-0 SI2C3P0 bit 0
R/W-1 U4ERIP2
Unimplemented: Read as `0' U4ERIP2:U4ERIP0: UART4 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' USB1IP2:USB1IP0: USB1 (USB OTG) Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' MI2C3P2:MI2C3P0: Master I2C3 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SI2C3P2:SI2C3P0: Slave I2C3 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled
bit 11 bit 10-8
bit 7 bit 6-4
bit 3 bit 2-0
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REGISTER 6-37:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 U4TXIP2 R/W-0 U4TXIP1 R/W-0 U4TXIP0 U-0 -- R/W-1 U4RXIP2 R/W-0 U4RXIP1
IPC22: INTERRUPT PRIORITY CONTROL REGISTER 22
R/W-0 SPI3IP1 R/W-0 SPI3IP0 U-0 -- R/W-1 SPF3IP2 R/W-0 SPF3IP1 R/W-0 SPF3IP0 bit 8 R/W-0 U4RXIP0 bit 0
R/W-1 SPI3IP2
Unimplemented: Read as `0' SPI3IP2:SP3IP0: SPI3 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SPF3IP2:SPF3IP0: SPI3 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' U4TXIP2:U4TXIP0: UART4 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' U4RXIP2:U4RXIP0: UART4 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled
bit 11 bit 10-8
bit 7 bit 6-4
bit 3 bit 2-0
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REGISTER 6-38:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 IC9IP2 R/W-0 IC9IP1 R/W-0 IC9IP0 U-0 -- R/W-1 OC9IP2 R/W-0 OC9IP1
IPC23: INTERRUPT PRIORITY CONTROL REGISTER 23
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 OC9IP0 bit 0
Unimplemented: Read as `0' IC9IP2:IC9IP0: Input Capture Channel 9 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' OC9IP2:OC9IP0: Output Compare Channel 9 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled
bit 3 bit 2-0
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6.4
6.4.1
1. 2.
Interrupt Setup Procedures
INITIALIZATION
6.4.3
TRAP SERVICE ROUTINE
To configure an interrupt source: Set the NSTDIS Control bit (INTCON1<15>) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source. If multiple priority levels are not desired, the IPCx register control bits for all enabled interrupt sources may be programmed to the same non-zero value. Note: At a device Reset, the IPCx registers are initialized, such that all user interrupt sources are assigned to priority level 4.
A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR.
6.4.4
INTERRUPT DISABLE
All user interrupts can be disabled using the following procedure: 1. 2. Push the current SR value onto the software stack using the PUSH instruction. Force the CPU to priority level 7 by inclusive ORing the value OEh with SRL.
To enable user interrupts, the POP instruction may be used to restore the previous SR value. Note that only user interrupts with a priority level of 7 or less can be disabled. Trap sources (level 8-15) cannot be disabled. The DISI instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction.
3. 4.
Clear the interrupt flag status bit associated with the peripheral in the associated IFSx register. Enable the interrupt source by setting the interrupt enable control bit associated with the source in the appropriate IECx register.
6.4.2
INTERRUPT SERVICE ROUTINE
The method that is used to declare an ISR and initialize the IVT with the correct vector address will depend on the programming language (i.e., `C' or assembler) and the language development toolsuite that is used to develop the application. In general, the user must clear the interrupt flag in the appropriate IFSx register for the source of the interrupt that the ISR handles. Otherwise, the ISR will be re-entered immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level.
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7.0
Note:
OSCILLATOR CONFIGURATION
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 6. Oscillator" (DS39700).
The oscillator system for PIC24FJ256GB110 family devices has the following features: * A total of four external and internal oscillator options as clock sources, providing 11 different clock modes
* An on-chip USB PLL block to provide a stable 48 MHz clock for the USB module as well as a range of frequency options for the system clock * Software-controllable switching between various clock sources * Software-controllable postscaler for selective clocking of CPU for system power savings * A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown * A separate and independently configurable system clock output for synchronizing external hardware A simplified diagram of the oscillator system is shown in Figure 7-1.
FIGURE 7-1:
PIC24FJ256GB110 FAMILY CLOCK DIAGRAM
PIC24FJ256GB110 Family
48 MHz USB Clock Primary Oscillator XT, HS, EC USB PLL XTPLL, HSPLL PLL & DIV ECPLL,FRCPLL REFOCON<15:8> Reference Clock Generator REFO
OSCO
OSCI
PLLDIV<2:0>
CPDIV<1:0> 8 MHz 4 MHz FRCDIV
FRC Oscillator
8 MHz (nominal)
Postscaler
Peripherals
CLKDIV<10:8>
FRC
CLKO
Postscaler
CPU
LPRC Oscillator
LPRC 31 kHz (nominal)
Secondary Oscillator SOSCO SOSCEN Enable Oscillator SOSC
CLKDIV<14:12>
SOSCI
Clock Control Logic Fail-Safe Clock Monitor
WDT, PWRT Clock Source Option for Other Modules
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7.1 CPU Clocking Scheme 7.2 Initial Configuration on POR
The system clock source can be provided by one of four sources: * Primary Oscillator (POSC) on the OSCI and OSCO pins * Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins * Fast Internal RC (FRC) Oscillator * Low-Power Internal RC (LPRC) Oscillator The primary oscillator and FRC sources have the option of using the internal USB PLL block, which generates both the USB module clock and a separate system clock from the 96 MHZ PLL. Refer to Section 7.5 "Oscillator Modes and USB Operation" for additional information. The internal FRC provides an 8 MHz clock source. It can optionally be reduced by the programmable clock divider to provide a range of system clock frequencies. The selected clock source generates the processor and peripheral clock sources. The processor clock source is divided by two to produce the internal instruction cycle clock, FCY. In this document, the instruction cycle clock is also denoted by FOSC/2. The internal instruction cycle clock, FOSC/2, can be provided on the OSCO I/O pin for some operating modes of the primary oscillator. The oscillator source (and operating mode) that is used at a device Power-on Reset event is selected using Configuration bit settings. The oscillator Configuration bit settings are located in the Configuration registers in the program memory (refer to Section 25.1 "Configuration Bits" for further details). The Primary Oscillator Configuration bits, POSCMD1:POSCMD0 (Configuration Word 2<1:0>), and the Initial Oscillator Select Configuration bits, FNOSC2:FNOSC0 (Configuration Word 2<10:8>), select the oscillator source that is used at a Power-on Reset. The FRC primary oscillator with postscaler (FRCDIV) is the default (unprogrammed) selection. The secondary oscillator, or one of the internal oscillators, may be chosen by programming these bit locations. The Configuration bits allow users to choose between the various clock modes, shown in Table 7-1.
7.2.1
CLOCK SWITCHING MODE CONFIGURATION BITS
The FCKSM Configuration bits (Configuration Word 2<7:6>) are used to jointly configure device clock switching and the Fail-Safe Clock Monitor (FSCM). Clock switching is enabled only when FCKSM1 is programmed (`0'). The FSCM is enabled only when FCKSM1:FCKSM0 are both programmed (`00').
TABLE 7-1:
CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Source Internal Internal Internal Secondary Primary Primary Primary Primary Primary Internal Internal POSCMD1: POSCMD0 11 xx 11 11 01 00 10 01 00 11 11 FNOSC2: FNOSC0 111 110 101 100 011 011 010 010 010 001 000 1 1 Note 1, 2 1 1 1
Oscillator Mode Fast RC Oscillator with Postscaler (FRCDIV) (Reserved) Low-Power RC Oscillator (LPRC) Secondary (Timer1) Oscillator (SOSC) Primary Oscillator (XT) with PLL Module (XTPLL) Primary Oscillator (EC) with PLL Module (ECPLL) Primary Oscillator (HS) Primary Oscillator (XT) Primary Oscillator (EC) Fast RC Oscillator with PLL Module (FRCPLL) Fast RC Oscillator (FRC) Note 1: 2:
OSCO pin function is determined by the OSCIOFCN Configuration bit. This is the default oscillator mode for an unprogrammed (erased) device.
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7.3 Control Registers
The operation of the oscillator is controlled by three Special Function Registers: * OSCCON * CLKDIV * OSCTUN The OSCCON register (Register 7-1) is the main control register for the oscillator. It controls clock source switching and allows the monitoring of clock sources. The CLKDIV register (Register 7-2) controls the features associated with Doze mode, as well as the postscaler for the FRC oscillator. The OSCTUN register (Register 7-3) allows the user to fine tune the FRC oscillator over a range of approximately 12%.
REGISTER 7-1:
U-0 -- bit 15 R/SO-0 CLKLOCK bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12
OSCCON: OSCILLATOR CONTROL REGISTER
R-0 COSC2 R-0 COSC1 R-0 COSC0 U-0 -- R/W-x(1) NOSC2 R/W-x(1) NOSC1 R/W-x(1) NOSC0 bit 8 R/W-0 R-0(3) LOCK U-0 -- R/CO-0 CF R/W-0 POSCEN R/W-0 SOSCEN R/W-0 OSWEN bit 0 CO = Clear Only bit W = Writable bit `1' = Bit is set SO = Set Only bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
IOLOCK(2)
Unimplemented: Read as `0' COSC2:COSC0: Current Oscillator Selection bits 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) Unimplemented: Read as `0' NOSC2:NOSC0: New Oscillator Selection bits(1) 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) Reset values for these bits are determined by the FNOSC Configuration bits. The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is `1', once the IOLOCK bit is set, it cannot be cleared. Also resets to `0' during any valid clock switch or whenever a non-PLL clock mode is selected.
bit 11 bit 10-8
Note 1: 2: 3:
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REGISTER 7-1:
bit 7
OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 = 1): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit. IOLOCK: I/O Lock Enable bit(2) 1 = I/O lock is active 0 = I/O lock is not active LOCK: PLL Lock Status bit(3) 1 = PLL module is in lock or PLL module start-up timer is satisfied 0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled Unimplemented: Read as `0' CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected POSCEN: Primary Oscillator Sleep Enable bit 1 = Primary oscillator continues to operate during Sleep mode 0 = Primary oscillator disabled during Sleep mode SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator OSWEN: Oscillator Switch Enable bit 1 = Initiate an oscillator switch to clock source specified by NOSC2:NOSC0 bits 0 = Oscillator switch is complete Reset values for these bits are determined by the FNOSC Configuration bits. The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is `1', once the IOLOCK bit is set, it cannot be cleared. Also resets to `0' during any valid clock switch or whenever a non-PLL clock mode is selected.
bit 6
bit 5
bit 4 bit 3
bit 2
bit 1
bit 0
Note 1: 2: 3:
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REGISTER 7-2:
R/W-0 ROI bit 15 R/W-0 CPDIV1 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 CPDIV0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
CLKDIV: CLOCK DIVIDER REGISTER
R/W-0 DOZE2 R/W-0 DOZE1 R/W-0 DOZE0 R/W-0 DOZEN(1) R/W-0 RCDIV2 R/W-0 RCDIV1 R/W-1 RCDIV0 bit 8
ROI: Recover on Interrupt bit 1 = Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1 0 = Interrupts have no effect on the DOZEN bit DOZE2:DOZE0: CPU Peripheral Clock Ratio Select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 DOZEN: DOZE Enable bit(1) 1 = DOZE2:DOZE0 bits specify the CPU peripheral clock ratio 0 = CPU peripheral clock ratio set to 1:1 RCDIV2:RCDIV0: FRC Postscaler Select bits 111 = 31.25 kHz (divide by 256) 110 = 125 kHz (divide by 64) 101 = 250 kHz (divide by 32) 100 = 500 kHz (divide by 16) 011 = 1 MHz (divide by 8) 010 = 2 MHz (divide by 4) 001 = 4 MHz (divide by 2) 000 = 8 MHz (divide by 1) CPDIV1:CPDIV0: USB System Clock Select bits (postscaler select from 32 MHz clock branch) 11 = 4 MHz (divide by 8)(2) 10 = 8 MHz (divide by 4)(2) 01 = 16 MHz (divide by 2) 00 = 32 MHz (divide by 1) Unimplemented: Read as `0' This bit is automatically cleared when the ROI bit is set and an interrupt occurs. This setting is not allowed while the USB module is enabled.
bit 14-12
bit 11
bit 10-8
bit 7-6
bit 5-0 Note 1: 2:
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REGISTER 7-3:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 TUN5(1) R/W-0 TUN4(1) R/W-0 TUN3(1) R/W-0 TUN2(1) R/W-0 TUN1(1)
OSCTUN: FRC OSCILLATOR TUNE REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 TUN0(1) bit 0
Unimplemented: Read as `0' TUN5:TUN0: FRC Oscillator Tuning bits 011111 = Maximum frequency deviation 011110 = * * * 000001 = 000000 = Center frequency, oscillator is running at factory calibrated frequency 111111 = * * * 100001 = 100000 = Minimum frequency deviation Increments or decrements of TUN5:TUN0 may not change the FRC frequency in equal steps over the FRC tuning range, and may not be monotonic.
Note 1:
7.4
Clock Switching Operation
7.4.1
ENABLING CLOCK SWITCHING
With few limitations, applications are free to switch between any of the four clock sources (POSC, SOSC, FRC and LPRC) under software control and at any time. To limit the possible side effects that could result from this flexibility, PIC24F devices have a safeguard lock built into the switching process. Note: The primary oscillator mode has three different submodes (XT, HS and EC) which are determined by the POSCMDx Configuration bits. While an application can switch to and from primary oscillator mode in software, it cannot switch between the different primary submodes without reprogramming the device.
To enable clock switching, the FCKSM1 Configuration bit in CW2 must be programmed to `0'. (Refer to Section 25.1 "Configuration Bits" for further details.) If the FCKSM1 Configuration bit is unprogrammed (`1'), the clock switching function and Fail-Safe Clock Monitor function are disabled. This is the default setting. The NOSCx control bits (OSCCON<10:8>) do not control the clock selection when clock switching is disabled. However, the COSCx bits (OSCCON<14:12>) will reflect the clock source selected by the FNOSCx Configuration bits. The OSWEN control bit (OSCCON<0>) has no effect when clock switching is disabled. It is held at `0' at all times.
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7.4.2 OSCILLATOR SWITCHING SEQUENCE
A recommended code sequence for a clock switch includes the following: 1. 2. Disable interrupts during the OSCCON register unlock and write sequence. Execute the unlock sequence for the OSCCON high byte by writing 78h and 9Ah to OSCCON<15:8> in two back-to-back instructions. Write new oscillator source to the NOSCx bits in the instruction immediately following the unlock sequence. Execute the unlock sequence for the OSCCON low byte by writing 46h and 57h to OSCCON<7:0> in two back-to-back instructions. Set the OSWEN bit in the instruction immediately following the unlock sequence. Continue to execute code that is not clock sensitive (optional). Invoke an appropriate amount of software delay (cycle counting) to allow the selected oscillator and/or PLL to start and stabilize. Check to see if OSWEN is `0'. If it is, the switch was successful. If OSWEN is still set, then check the LOCK bit to determine the cause of failure. At a minimum, performing a clock switch requires this basic sequence: 1. If desired, read the COSCx bits (OSCCON<14:12>), to determine the current oscillator source. Perform the unlock sequence to allow a write to the OSCCON register high byte. Write the appropriate value to the NOSCx bits (OSCCON<10:8>) for the new oscillator source. Perform the unlock sequence to allow a write to the OSCCON register low byte. Set the OSWEN bit to initiate the oscillator switch.
2. 3. 4. 5.
3.
4.
5. 6. 7.
Once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. The clock switching hardware compares the COSCx bits with the new value of the NOSCx bits. If they are the same, then the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. If a valid clock switch has been initiated, the LOCK (OSCCON<5>) and CF (OSCCON<3>) bits are cleared. The new oscillator is turned on by the hardware if it is not currently running. If a crystal oscillator must be turned on, the hardware will wait until the OST expires. If the new source is using the PLL, then the hardware waits until a PLL lock is detected (LOCK = 1). The hardware waits for 10 clock cycles from the new clock source and then performs the clock switch. The hardware clears the OSWEN bit to indicate a successful clock transition. In addition, the NOSCx bit values are transferred to the COSCx bits. The old clock source is turned off at this time, with the exception of LPRC (if WDT or FSCM are enabled) or SOSC (if SOSCEN remains set). Note 1: The processor will continue to execute code throughout the clock switching sequence. Timing sensitive code should not be executed during this time. 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes.
8.
2.
3.
The core sequence for unlocking the OSCCON register and initiating a clock switch is shown in Example 7-1.
EXAMPLE 7-1:
BASIC CODE SEQUENCE FOR CLOCK SWITCHING
4.
5.
6.
;Place the new oscillator selection in W0 ;OSCCONH (high byte) Unlock Sequence MOV #OSCCONH, w1 MOV #0x78, w2 MOV #0x9A, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Set new oscillator selection MOV.b WREG, OSCCONH ;OSCCONL (low byte) unlock sequence MOV #OSCCONL, w1 MOV #0x46, w2 MOV #0x57, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Start oscillator switch operation BSET OSCCON,#0
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7.5 Oscillator Modes and USB Operation
TABLE 7-2: SYSTEM CLOCK OPTIONS DURING USB OPERATION
Microcontroller Clock Frequency 32 MHz 16 MHz 8 MHz 4 MHz MCU Clock Division (CPDIV1:CPDIV0) None (00) /2 (01) /4 (10) /8 (11)
Because of the timing requirements imposed by USB, an internal clock of 48 MHz is required at all times while the USB module is enabled. Since this is well beyond the maximum CPU clock speed, a method is provided to internally generate both the USB and system clocks from a single oscillator source. PIC24FJ256GB110 family devices use the same clock structure as other PIC24FJ devices, but include a two-branch PLL system to generate the two clock signals. The USB PLL block is shown in Figure 7-2. In this system, the input from the primary oscillator is divided down by a PLL prescaler to generate a 4 MHz output. This is used to drive an on-chip 96 MHz PLL frequency multiplier to drive the two clock branches. One branch uses a fixed divide-by-2 frequency divider to generate the 48 MHz USB clock. The other branch uses a fixed divide-by-3 frequency divider and configurable PLL prescaler/divider to generate a range of system clock frequencies. The CPDIV bits select the system clock speed; available clock options are listed in Table 7-2. The USB PLL prescaler does not automatically sense the incoming oscillator frequency. The user must manually configure the PLL divider to generate the required 4 MHz output, using the PLLDIV2:PLLDIV0 Configuration bits. This limits the choices for primary oscillator frequency to a total of 8 possibilities, shown in Table 7-3.
TABLE 7-3:
VALID PRIMARY OSCILLATOR CONFIGURATIONS FOR USB OPERATIONS
Clock Mode ECPLL ECPLL HSPLL, ECPLL HSPLL, ECPLL HSPLL, ECPLL HSPLL, ECPLL HSPLL, ECPLL HSPLL, ECPLL, XTPLL PLL Division (PLLDIV2: PLLDIV0) /12 (111) /10 (110) /6 (101) /5 (100) /4 (011) /3 (010) /2 (001) /1 (000)
Input Oscillator Frequency 48 MHz 40 MHz 24 MHz 20 MHz 16 MHz 12 MHz 8 MHz 4 MHz
FIGURE 7-2:
USB PLL BLOCK
PLLDIV2:PLLDIV0
FNOSC2:FNOSC0 Input from POSC Input from FRC (4 MHz or 8 MHz)
/3
32 MHz
PLL Prescaler
/ 12 / 10 /6 /5 /4 /3 /2 /1
111 110 101 100 011 010 001 000
/2 4 MHz 96 MHz PLL
48 MHz Clock for USB Module
PLL Prescaler
/8 /4 /2 /1
11 10 01 00
PLL Output for System Clock
CPDIV1:CPDIV0
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7.5.1 CONSIDERATIONS FOR USB OPERATION
7.6
Reference Clock Output
When using the USB On-The-Go module in PIC24FJ256GB110 family devices, users must always observe these rules in configuring the system clock: * For USB operation, the selected clock source (EC, HS or XT) must meet the USB clock tolerance requirements. * The Primary Oscillator/PLL modes are the only oscillator configurations that permit USB operation. There is no provision to provide a separate external clock source to the USB module. * While the FRCPLL Oscillator mode is available in these devices, it should never be used for USB applications. FRCPLL mode is still available when the application is not using the USB module. However, the user must always ensure that the FRC source is configured to provide a frequency of 4 MHz or 8 MHz (RCDIV2:RCDIV0 = 001 or 000), and that the USB PLL prescaler is configured appropriately. * All other oscillator modes are available; however, USB operation is not possible when these modes are selected. They may still be useful in cases where other power levels of operation are desirable and the USB module is not needed (e.g., the application is sleeping and waiting for bus attachment).
In addition to the CLKO output (FOSC/2) available in certain oscillator modes, the device clock in the PIC24FJ256GB110 family devices can also be configured to provide a reference clock output signal to a port pin. This feature is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application. This reference clock output is controlled by the REFOCON register (Register 7-4). Setting the ROEN bit (REFOCON<15>) makes the clock signal available on the REFO pin. The RODIV bits (REFOCON<11:8>) enable the selection of 16 different clock divider options. The ROSSLP and ROSEL bits (REFOCON<13:12>) control the availability of the reference output during Sleep mode. The ROSEL bit determines if the oscillator on OSC1 and OSC2, or the current system clock source, is used for the reference clock output. The ROSSLP bit determines if the reference source is available on REFO when the device is in Sleep mode. To use the reference clock output in Sleep mode, both the ROSSLP and ROSEL bits must be set. The device clock must also be configured for one of the primary modes (EC, HS or XT); otherwise, if the POSCEN bit is not also set, the oscillator on OSC1 and OSC2 will be powered down when the device enters Sleep mode. Clearing the ROSEL bit allows the reference output frequency to change as the system clock changes during any clock switches.
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REGISTER 7-4:
R/W-0 ROEN bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER
U-0 -- R/W-0 ROSSLP R/W-0 ROSEL R/W-0 RODIV3 R/W-0 RODIV2 R/W-0 RODIV1 R/W-0 RODIV0 bit 8
ROEN: Reference Oscillator Output Enable bit 1 = Reference oscillator enabled on REFO pin 0 = Reference oscillator disabled Unimplemented: Read as `0' ROSSLP: Reference Oscillator Output Stop in Sleep bit 1 = Reference oscillator continues to run in Sleep 0 = Reference oscillator is disabled in Sleep ROSEL: Reference Oscillator Source Select bit 1 = Primary oscillator used as the base clock. Note that the crystal oscillator must be enabled using the FOSC2:FOSC0 bits; crystal maintains the operation in Sleep mode. 0 = System clock used as the base clock; base clock reflects any clock switching of the device RODIV3:RODIV0: Reference Oscillator Divisor Select bits 1111 = Base clock value divided by 32,768 1110 = Base clock value divided by 16,384 1101 = Base clock value divided by 8,192 1100 = Base clock value divided by 4,096 1011 = Base clock value divided by 2,048 1010 = Base clock value divided by 1,024 1001 = Base clock value divided by 512 1000 = Base clock value divided by 256 0111 = Base clock value divided by 128 0110 = Base clock value divided by 64 0101 = Base clock value divided by 32 0100 = Base clock value divided by 16 0011 = Base clock value divided by 8 0010 = Base clock value divided by 4 0001 = Base clock value divided by 2 0000 = Base clock value Unimplemented: Read as `0'
bit 14 bit 13
bit 12
bit 11-8
bit 7-0
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8.0
Note:
POWER-SAVING FEATURES
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 10. Power-Saving Features" (DS39698).
Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When the device exits these modes, it is said to "wake-up". Note: SLEEP_MODE and IDLE_MODE are constants defined in the assembler include file for the selected device.
8.2.1
SLEEP MODE
The PIC24FJ256GB110 family of devices provides the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. All PIC24F devices manage power consumption in four different ways: * * * * Clock frequency Instruction-based Sleep and Idle modes Software controlled Doze mode Selective peripheral control in software
Sleep mode has these features: * The system clock source is shut down. If an on-chip oscillator is used, it is turned off. * The device current consumption will be reduced to a minimum provided that no I/O pin is sourcing current. * The Fail-Safe Clock Monitor does not operate during Sleep mode since the system clock source is disabled. * The LPRC clock will continue to run in Sleep mode if the WDT is enabled. * The WDT, if enabled, is automatically cleared prior to entering Sleep mode. * Some device features or peripherals may continue to operate in Sleep mode. This includes items such as the input change notification on the I/O ports, or peripherals that use an external clock input. Any peripheral that requires the system clock source for its operation will be disabled in Sleep mode. The device will wake-up from Sleep mode on any of the these events: * On any interrupt source that is individually enabled * On any form of device Reset * On a WDT time-out On wake-up from Sleep, the processor will restart with the same clock source that was active when Sleep mode was entered.
Combinations of these methods can be used to selectively tailor an application's power consumption, while still maintaining critical application features, such as timing-sensitive communications.
8.1
Clock Frequency and Clock Switching
PIC24F devices allow for a wide range of clock frequencies to be selected under application control. If the system clock configuration is not locked, users can choose low-power or high-precision oscillators by simply changing the NOSC bits. The process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in Section 7.0 "Oscillator Configuration".
8.2
Instruction-Based Power-Saving Modes
PIC24F devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction. Sleep mode stops clock operation and halts all code execution; Idle mode halts the CPU and code execution, but allows peripheral modules to continue operation. The assembly syntax of the PWRSAV instruction is shown in Example 8-1.
EXAMPLE 8-1:
PWRSAV PWRSAV
PWRSAV INSTRUCTION SYNTAX
; Put the device into SLEEP mode ; Put the device into IDLE mode
#SLEEP_MODE #IDLE_MODE
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8.2.2 IDLE MODE
Idle mode has these features: * The CPU will stop executing instructions. * The WDT is automatically cleared. * The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 8.4 "Selective Peripheral Module Control"). * If the WDT or FSCM is enabled, the LPRC will also remain active. The device will wake from Idle mode on any of these events: * Any interrupt that is individually enabled. * Any device Reset. * A WDT time-out. On wake-up from Idle, the clock is reapplied to the CPU and instruction execution begins immediately, starting with the instruction following the PWRSAV instruction or the first instruction in the ISR. It is also possible to use Doze mode to selectively reduce power consumption in event driven applications. This allows clock sensitive functions, such as synchronous communications, to continue without interruption while the CPU Idles, waiting for something to invoke an interrupt routine. Enabling the automatic return to full-speed CPU operation on interrupts is enabled by setting the ROI bit (CLKDIV<15>). By default, interrupt events have no effect on Doze mode operation.
8.4
Selective Peripheral Module Control
Idle and Doze modes allow users to substantially reduce power consumption by slowing or stopping the CPU clock. Even so, peripheral modules still remain clocked and thus consume power. There may be cases where the application needs what these modes do not provide: the allocation of power resources to CPU processing with minimal power consumption from the peripherals. PIC24F devices address this requirement by allowing peripheral modules to be selectively disabled, reducing or eliminating their power consumption. This can be done with two control bits: * The Peripheral Enable bit, generically named, "XXXEN", located in the module's main control SFR. * The Peripheral Module Disable (PMD) bit, generically named, "XXXMD", located in one of the PMD control registers. Both bits have similar functions in enabling or disabling its associated module. Setting the PMD bit for a module disables all clock sources to that module, reducing its power consumption to an absolute minimum. In this state, the control and status registers associated with the peripheral will also be disabled, so writes to those registers will have no effect and read values will be invalid. Many peripheral modules have a corresponding PMD bit. In contrast, disabling a module by clearing its XXXEN bit disables its functionality, but leaves its registers available to be read and written to. This reduces power consumption, but not by as much as setting the PMD bit does. Most peripheral modules have an enable bit; exceptions include input capture, output compare and RTCC. To achieve more selective power savings, peripheral modules can also be selectively disabled when the device enters Idle mode. This is done through the control bit of the generic name format, "XXXIDL". By default, all modules that can operate during Idle mode will do so. Using the disable on Idle feature allows further reduction of power consumption during Idle mode, enhancing power savings for extremely critical power applications.
8.2.3
INTERRUPTS COINCIDENT WITH POWER SAVE INSTRUCTIONS
Any interrupt that coincides with the execution of a PWRSAV instruction will be held off until entry into Sleep or Idle mode has completed. The device will then wake-up from Sleep or Idle mode.
8.3
Doze Mode
Generally, changing clock speed and invoking one of the power-saving modes are the preferred strategies for reducing power consumption. There may be circumstances, however, where this is not practical. For example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else. Reducing system clock speed may introduce communication errors, while using a power-saving mode may stop communications completely. Doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. In this mode, the system clock continues to operate from the same source and at the same speed. Peripheral modules continue to be clocked at the same speed while the CPU clock speed is reduced. Synchronization between the two clock domains is maintained, allowing the peripherals to access the SFRs while the CPU executes code at a slower rate. Doze mode is enabled by setting the DOZEN bit (CLKDIV<11>). The ratio between peripheral and core clock speed is determined by the DOZE2:DOZE0 bits (CLKDIV<14:12>). There are eight possible configurations, from 1:1 to 1:256, with 1:1 being the default.
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9.0
Note:
I/O PORTS
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 12. I/O Ports with Peripheral Pin Select (PPS)" (DS39711).
peripheral that shares the same pin. Figure 9-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected. When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled. If a peripheral is enabled, but the peripheral is not actively driving a pin, that pin may be driven by a port. All port pins have three registers directly associated with their operation as digital I/O. The Data Direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is a `1', then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the Output Latch register (LATx), read the latch. Writes to the latch, write the latch. Reads from the port (PORTx), read the port pins, while writes to the port pins, write the latch. Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros.
All of the device pins (except VDD, VSS, MCLR and OSCI/CLKI) are shared between the peripherals and the parallel I/O ports. All I/O input ports feature Schmitt Trigger inputs for improved noise immunity.
9.1
Parallel I/O (PIO) Ports
A parallel I/O port that shares a pin with a peripheral is, in general, subservient to the peripheral. The peripheral's output buffer data and control signals are provided to a pair of multiplexers. The multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the I/O pin. The logic also prevents "loop through", in which a port's digital output can drive the input of a
FIGURE 9-1:
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Peripheral Module
Peripheral Input Data Peripheral Module Enable Peripheral Output Enable Peripheral Output Data 1 0 1 0 Output Enable
Output Multiplexers
I/O
PIO Module
Read TRIS
Output Data
Data Bus WR TRIS
D CK
Q
I/O Pin
TRIS Latch D WR LAT + WR PORT CK Data Latch Q
Read LAT Input Data Read PORT
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9.1.1 OPEN-DRAIN CONFIGURATION
9.3
Input Change Notification
In addition to the PORT, LAT and TRIS registers for data control, each port pin can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The open-drain feature allows the generation of outputs higher than VDD (e.g., 5V) on any desired digital only pins by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification.
The input change notification function of the I/O ports allows the PIC24FJ256GB110 family of devices to generate interrupt requests to the processor in response to a change of state on selected input pins. This feature is capable of detecting input change of states even in Sleep mode, when the clocks are disabled. Depending on the device pin count, there are up to 81 external inputs that may be selected (enabled) for generating an interrupt request on a change of state. Registers CNEN1 through CNEN6 contain the interrupt enable control bits for each of the CN input pins. Setting any of these bits enables a CN interrupt for the corresponding pins. Each CN pin has a both a weak pull-up and a weak pull-down connected to it. The pull-ups act as a current source that is connected to the pin, while the pull-downs act as a current sink that is connected to the pin. These eliminate the need for external resistors when push button or keypad devices are connected. The pull-ups and pull-downs are separately enabled using the CNPU1 through CNPU6 registers (for pull-ups) and the CNPD1 through CNPD6 registers (for pull-downs). Each CN pin has individual control bits for its pull-up and pull-down. Setting a control bit enables the weak pull-up or pull-down for the corresponding pin. When the internal pull-up is selected, the pin pulls up to VDD - 0.7V (typical). Make sure that there is no external pull-up source when the internal pull-ups are enabled, as the voltage difference can cause a current path. Note: Pull-ups on change notification pins should always be disabled whenever the port pin is configured as a digital output.
9.2
Configuring Analog Port Pins
The AD1PCFGL and TRIS registers control the operation of the A/D port pins. Setting a port pin as an analog input also requires that the corresponding TRIS bit be set. If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. When reading the PORT register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will not convert an analog input. Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications.
9.2.1
I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically, this instruction would be a NOP.
EXAMPLE 9-1:
MOV MOV NOP BTSS 0xFF00, W0 W0, TRISBB PORTB, #13
PORT WRITE/READ EXAMPLE
; ; ; ; Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs Delay 1 cycle Next Instruction
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9.4 Peripheral Pin Select
9.4.2 AVAILABLE PERIPHERALS
A major challenge in general purpose devices is providing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. In an application that needs to use more than one peripheral multiplexed on a single pin, inconvenient workarounds in application code or a complete redesign may be the only option. The peripheral pin select feature provides an alternative to these choices by enabling the user's peripheral set selection and their placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, users can better tailor the microcontroller to their entire application, rather than trimming the application to fit the device. The peripheral pin select feature operates over a fixed subset of digital I/O pins. Users may independently map the input and/or output of any one of many digital peripherals to any one of these I/O pins. Peripheral pin select is performed in software and generally does not require the device to be reprogrammed. Hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping once it has been established. The peripherals managed by the peripheral pin select are all digital only peripherals. These include general serial communications (UART and SPI), general purpose timer clock inputs, timer related peripherals (input capture and output compare) and external interrupt inputs. Also included are the outputs of the comparator module, since these are discrete digital signals. Peripheral pin select is not available for I2CTM change notification inputs, RTCC alarm outputs or peripherals with analog inputs. A key difference between pin select and non pin select peripherals is that pin select peripherals are not associated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used. In contrast, non pin select peripherals are always available on a default pin, assuming that the peripheral is active and not conflicting with another peripheral.
9.4.2.1
Peripheral Pin Select Function Priority
9.4.1
AVAILABLE PINS
The peripheral pin select feature is used with a range of up to 44 pins, depending on the particular device and its pin count. Pins that support the peripheral pin select feature include the designation "RPn" or "RPIn" in their full pin designation, where "n" is the remappable pin number. "RP" is used to designate pins that support both remappable input and output functions, while "RPI" indicates pins that support remappable input functions only. PIC24FJ256GB110 family devices support a larger number of remappable input only pins than remappable input/output pins. In this device family, there are up to 32 remappable input/output pins, depending on the pin count of the particular device selected; these are numbered RP0 through RP31. Remappable input only pins are numbered above this range, from RPI32 to RPI43 (or the upper limit for that particular device). See Table 1-4 for a summary of pinout options in each package offering.
When a pin selectable peripheral is active on a given I/O pin, it takes priority over all other digital I/O and digital communication peripherals associated with the pin. Priority is given regardless of the type of peripheral that is mapped. Pin select peripherals never take priority over any analog functions associated with the pin.
9.4.3
CONTROLLING PERIPHERAL PIN SELECT
Peripheral pin select features are controlled through two sets of Special Function Registers: one to map peripheral inputs, and one to map outputs. Because they are separately controlled, a particular peripheral's input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. The association of a peripheral to a peripheral selectable pin is handled in two different ways, depending on if an input or an output is being mapped.
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9.4.3.1 Input Mapping
The inputs of the peripheral pin select options are mapped on the basis of the peripheral; that is, a control register associated with a peripheral dictates the pin it will be mapped to. The RPINRx registers are used to configure peripheral input mapping (see Register 9-1 through Register 9-21). Each register contains two sets of 6-bit fields, with each set associated with one of the pin selectable peripherals. Programming a given peripheral's bit field with an appropriate 6-bit value maps the RPn pin with that value to that peripheral. For any given device, the valid range of values for any of the bit fields corresponds to the maximum number of peripheral pin selections supported by the device.
TABLE 9-1:
SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1)
Function Name INT1 INT2 INT3 INT4 IC1 IC2 IC3 IC4 IC5 IC6 IC7 IC8 IC9 OCFA OCFB SCK1IN SDI1 SS1IN SCK2IN SDI2 SS2IN SCK3IN SDI3 SS3IN T1CK T2CK T3CK T4CK T5CK U1CTS U1RX U2CTS U2RX U3CTS U3RX U4CTS U4RX Register RPINR0 RPINR1 RPINR1 RPINR2 RPINR7 RPINR7 RPINR8 RPINR8 RPINR9 RPINR9 RPINR10 RPINR10 RPINR15 RPINR11 RPINR11 RPINR20 RPINR20 RPINR21 RPINR22 RPINR22 RPINR23 RPINR23 RPINR28 RPINR29 RPINR2 RPINR3 RPINR3 RPINR4 RPINR4 RPINR18 RPINR18 RPINR19 RPINR19 RPINR21 RPINR17 RPINR27 RPINR27 Function Mapping Bits INT1R5:INT1R0 INT2R5:INT2R0 INT3R5:INT3R0 INT4R5:INT4R0 IC1R5:IC1R0 IC2R5:IC2R0 IC3R5:IC3R0 IC4R5:IC4R0 IC5R5:IC5R0 IC6R5:IC6R0 IC7R5:IC7R0 IC8R5:IC8R0 IC9R5:IC9R0 OCFAR5:OCFAR0 OCFBR5:OCFBR0 SCK1R5:SCK1R0 SDI1R5:SDI1R0 SS1R5:SS1R0 SCK2R5:SCK2R0 SDI2R5:SDI2R0 SS2R5:SS2R0 SCK3R5:SCK3R0 SDI3R5:SDI3R0 SS3R5:SS3R0 T1CKR5:T1CKR0 T2CKR5:T2CKR0 T3CKR5:T3CKR0 T4CKR5:T4CKR0 T5CKR5:T5CKR0 U1CTSR5:U1CTSR0 U1RXR5:U1RXR0 U2CTSR5:U2CTSR0 U2RXR5:U2RXR0 U3CTSR5:U3CTSR0 U3RXR5:U3RXR0 U4CTSR5:U4CTSR0 U4RXR5:U4RXR0
Input Name External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 Input Capture 1 Input Capture 2 Input Capture 3 Input Capture 4 Input Capture 5 Input Capture 6 Input Capture 7 Input Capture 8 Input Capture 9 Output Compare Fault A Output Compare Fault B SPI1 Clock Input SPI1 Data Input SPI1 Slave Select Input SPI2 Clock Input SPI2 Data Input SPI2 Slave Select Input SPI3 Clock Input SPI3 Data Input SPI3 Slave Select Input Timer1 External Clock Timer2 External Clock Timer3 External Clock Timer4 External Clock Timer5 External Clock UART1 Clear To Send UART1 Receive UART2 Clear To Send UART2 Receive UART3 Clear To Send UART3 Receive UART4 Clear To Send UART4 Receive Note 1:
Unless otherwise noted, all inputs use the Schmitt Trigger input buffers.
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9.4.3.2 Output Mapping
In contrast to inputs, the outputs of the peripheral pin select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping. Each register contains two 6-bit fields, with each field being associated with one RPn pin (see Register 9-22 through Register 9-37). The value of the bit field corresponds to one of the peripherals and that peripheral's output is mapped to the pin (see Table 9-2). Because of the mapping technique, the list of peripherals for output mapping also includes a null value of `000000'. This permits any given pin to remain disconnected from the output of any of the pin selectable peripherals.
TABLE 9-2:
SELECTABLE OUTPUT SOURCES (MAPS FUNCTION TO OUTPUT)
Function NULL(2) C1OUT C2OUT U1TX U1RTS U2RTS
(3)
Output Function Number(1) 0 1 2 3 4 5 6 7 8 9 10 11 12 18 19 20 21 22 23 24 25 28 29 30 31 32 33 34 35 37-63 Note 1: 2: 3:
Output Name Null Comparator 1 Output Comparator 2 Output UART1 Transmit UART1 Request To Send UART2 Transmit UART2 Request To Send SPI1 Data Output SPI1 Clock Output SPI1 Slave Select Output SPI2 Data Output SPI2 Clock Output SPI2 Slave Select Output Output Compare 1 Output Compare 2 Output Compare 3 Output Compare 4 Output Compare 5 Output Compare 6 Output Compare 7 Output Compare 8 UART3 Transmit UART3 Request To Send UART4 Transmit UART4 Request To Send SPI3 Data Output SPI3 Clock Output SPI3 Slave Select Output Output Compare 9 NC
U2TX
(3)
SDO1 SCK1OUT SS1OUT SDO2 SCK2OUT SS2OUT OC1 OC2 OC3 OC4 OC5 OC6 OC7 OC8 U3TX U3RTS
(3)
U4TX U4RTS(3) SDO3 SCK3OUT SS3OUT OC9 (unused)
Setting the RPORx register with the listed value assigns that output function to the associated RPn pin. The NULL function is assigned to all RPn outputs at device Reset and disables the RPn output function. IrDA(R) BCLK functionality uses this output.
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9.4.3.3 Mapping Limitations 9.4.4.1 Control Register Lock
The control schema of the peripheral pin select is extremely flexible. Other than systematic blocks that prevent signal contention caused by two physical pins being configured as the same functional input or two functional outputs configured as the same pin, there are no hardware enforced lock outs. The flexibility extends to the point of allowing a single input to drive multiple peripherals or a single functional output to drive multiple output pins. Under normal operation, writes to the RPINRx and RPORx registers are not allowed. Attempted writes will appear to execute normally, but the contents of the registers will remain unchanged. To change these registers, they must be unlocked in hardware. The register lock is controlled by the IOLOCK bit (OSCCON<6>). Setting IOLOCK prevents writes to the control registers; clearing IOLOCK allows writes. To set or clear IOLOCK, a specific command sequence must be executed: 1. 2. 3. Write 46h to OSCCON<7:0>. Write 57h to OSCCON<7:0>. Clear (or set) IOLOCK as a single operation.
9.4.3.4
Mapping Exceptions for PIC24FJ256GB110 Family Devices
Although the PPS registers theoretically allow for up to 64 remappable I/O pins, not all of these are implemented in all devices. For PIC24FJ256GB110 family devices, the maximum number of remappable pins available are 44, which includes 12 input only pins. In addition, some pins in the RP and RPI sequences are unimplemented in lower pin count devices. The differences in available remappable pins are summarized in Table 9-3. When developing applications that use remappable pins, users should also keep these things in mind: * For the RPINRx registers, bit combinations corresponding to an unimplemented pin for a particular device are treated as invalid; the corresponding module will not have an input mapped to it. For all PIC24FJ256GB110 family devices, this includes all values greater than 43 (`101011'). * For RPORx registers, the bit fields corresponding to an unimplemented pin will also be unimplemented. Writing to these fields will have no effect.
Unlike the similar sequence with the oscillator's LOCK bit, IOLOCK remains in one state until changed. This allows all of the peripheral pin selects to be configured with a single unlock sequence followed by an update to all control registers, then locked with a second lock sequence.
9.4.4.2
Continuous State Monitoring
In addition to being protected from direct writes, the contents of the RPINRx and RPORx registers are constantly monitored in hardware by shadow registers. If an unexpected change in any of the registers occurs (such as cell disturbances caused by ESD or other external events), a Configuration Mismatch Reset will be triggered.
9.4.4.3
Configuration Bit Pin Select Lock
9.4.4
CONTROLLING CONFIGURATION CHANGES
Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. PIC24F devices include three features to prevent alterations to the peripheral map: * Control register lock sequence * Continuous state monitoring * Configuration bit remapping lock
As an additional level of safety, the device can be configured to prevent more than one write session to the RPINRx and RPORx registers. The IOL1WAY (CW2<4>) Configuration bit blocks the IOLOCK bit from being cleared after it has been set once. If IOLOCK remains set, the register unlock procedure will not execute and the Peripheral Pin Select Control registers cannot be written to. The only way to clear the bit and re-enable peripheral remapping is to perform a device Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Programming IOL1WAY allows users unlimited access (with the proper use of the unlock sequence) to the peripheral pin select registers.
TABLE 9-3:
REMAPPABLE PIN EXCEPTIONS FOR PIC24FJ256GB110 FAMILY DEVICES
RP Pins (I/O) Total 28 31 32 Unimplemented RP5, RP15, RP30, RP31 RP31 -- Total 1 9 12 RPI Pins Unimplemented RPI32-36, RPI38-43 RPI32, RPI39, RPI41 --
Device Pin Count 64-pin 80-pin 100-pin
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9.4.5 CONSIDERATIONS FOR PERIPHERAL PIN SELECTION
The ability to control peripheral pin selection introduces several considerations into application design that could be overlooked. This is particularly true for several common peripherals that are available only as remappable peripherals. The main consideration is that the peripheral pin selects are not available on default pins in the device's default (Reset) state. Since all RPINRx registers reset to `111111' and all RPORx registers reset to `000000', all peripheral pin select inputs are tied to VSS and all peripheral pin select outputs are disconnected. Note: In tying peripheral pin select inputs to RP63, RP63 does not have to exist on a device for the registers to be reset to it. Along these lines, configuring a remappable pin for a specific peripheral does not automatically turn that feature on. The peripheral must be specifically configured for operation and enabled, as if it were tied to a fixed pin. Where this happens in the application code (immediately following device Reset and peripheral configuration or inside the main application routine) depends on the peripheral and its use in the application. A final consideration is that peripheral pin select functions neither override analog inputs, nor reconfigure pins with analog functions for digital I/O. If a pin is configured as an analog input on device Reset, it must be explicitly reconfigured as digital I/O when used with a peripheral pin select. Example 9-2 shows a configuration for bidirectional communication with flow control using UART1. The following input and output functions are used: * Input Functions: U1RX, U1CTS * Output Functions: U1TX, U1RTS
This situation requires the user to initialize the device with the proper peripheral configuration before any other application code is executed. Since the IOLOCK bit resets in the unlocked state, it is not necessary to execute the unlock sequence after the device has come out of Reset. For application safety, however, it is best to set IOLOCK and lock the configuration after writing to the control registers. Because the unlock sequence is timing critical, it must be executed as an assembly language routine in the same manner as changes to the oscillator configuration. If the bulk of the application is written in C or another high-level language, the unlock sequence should be performed by writing inline assembly. Choosing the configuration requires the review of all peripheral pin selects and their pin assignments, especially those that will not be used in the application. In all cases, unused pin-selectable peripherals should be disabled completely. Unused peripherals should have their inputs assigned to an unused RPn pin function. I/O pins with unused RPn functions should be configured with the null peripheral output. The assignment of a peripheral to a particular pin does not automatically perform any other configuration of the pin's I/O circuitry. In theory, this means adding a pin-selectable output to a pin may mean inadvertently driving an existing peripheral input when the output is driven. Users must be familiar with the behavior of other fixed peripherals that share a remappable pin and know when to enable or disable them. To be safe, fixed digital peripherals that share the same pin should be disabled when not in use.
EXAMPLE 9-2:
CONFIGURING UART1 INPUT AND OUTPUT FUNCTIONS
\n" \n" \n" \n" \n"
// Unlock Registers asm volatile ( "MOV #OSCCON, w1 "MOV #0x46, w2 "MOV #0x57, w3 "MOV.b w2, [w1] "MOV.b w3, [w1] "BCLR OSCCON,#6");
// Configure Input Functions (Table 9-1)) // Assign U1RX To Pin RP0 RPINR18bits.U1RXR = 0; // Assign U1CTS To Pin RP1 RPINR18bits.U1CTSR = 1; // Configure Output Functions (Table 9-2) // Assign U1TX To Pin RP2 RPOR1bits.RP2R = 3; // Assign U1RTS To Pin RP3 RPOR1bits.RP3R = 4; // Lock Registers asm volatile ( "MOV "MOV "MOV "MOV.b "MOV.b "BSET
#OSCCON, w1 #0x46, w2 #0x57, w3 w2, w3, OSCCON, #6"
\n" \n" \n" \n" \n" );
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9.4.6 PERIPHERAL PIN SELECT REGISTERS
Note: The PIC24FJ256GB110 family of devices implements a total of 37 registers for remappable peripheral configuration: * Input Remappable Peripheral Registers (21) * Output Remappable Peripheral Registers (16) Input and output register values can only be changed if IOLOCK (OSCCON<6>) = 0. See Section 9.4.4.1 "Control Register Lock" for a specific command sequence.
REGISTER 9-1:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-0
RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
U-0 -- R/W-1 INT1R5 R/W-1 INT1R4 R/W-1 INT1R3 R/W-1 INT1R2 R/W-1 INT1R1 R/W-1 INT1R0 bit 8 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' INT1R5:INT1R0: Assign External Interrupt 1 (INT1) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0'
REGISTER 9-2:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0
RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1
U-0 -- R/W-1 INT3R5 R/W-1 INT3R4 R/W-1 INT3R3 R/W-1 INT3R2 R/W-1 INT3R1 R/W-1 INT3R0 bit 8 U-0 -- R/W-1 INT2R5 R/W-1 INT2R4 R/W-1 INT2R3 R/W-1 INT2R2 R/W-1 INT2R1 R/W-1 INT2R0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' INT3R5:INT3R0: Assign External Interrupt 3 (INT3) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' INT2R5:INT2R0: Assign External Interrupt 2 (INT2) to Corresponding RPn or RPIn Pin bits
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REGISTER 9-3:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 INT4R5 R/W-1 INT4R4 R/W-1 INT4R3 R/W-1 INT4R2 R/W-1 INT4R1
RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2
U-0 -- R/W-1 T1CKR5 R/W-1 T1CKR4 R/W-1 T1CKR3 R/W-1 T1CKR2 R/W-1 T1CKR1 R/W-1 T1CKR0 bit 8 R/W-1 INT4R0 bit 0
Unimplemented: Read as `0' T1CKR5:T1CKR0: Assign Timer1 External Clock (T1CK) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' INT4R5:INT4R0: Assign External Interrupt 4 (INT4) to Corresponding RPn or RPIn Pin bits
REGISTER 9-4:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0
RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3
U-0 -- R/W-1 T3CKR5 R/W-1 T3CKR4 R/W-1 T3CKR3 R/W-1 T3CKR2 R/W-1 T3CKR1 R/W-1 T3CKR0 bit 8 U-0 -- R/W-1 T2CKR5 R/W-1 T2CKR4 R/W-1 T2CKR3 R/W-1 T2CKR2 R/W-1 T2CKR1 R/W-1 T2CKR0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' T3CKR5:T3CKR0: Assign Timer3 External Clock (T3CK) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' T2CKR5:T2CKR0: Assign Timer2 External Clock (T2CK) to Corresponding RPn or RPIn Pin bits
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REGISTER 9-5:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 T4CKR5 R/W-1 T4CKR4 R/W-1 T4CKR3 R/W-1 T4CKR2 R/W-1 T4CKR1
RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4
U-0 -- R/W-1 T5CKR5 R/W-1 T5CKR4 R/W-1 T5CKR3 R/W-1 T5CKR2 R/W-1 T5CKR1 R/W-1 T5CKR0 bit 8 R/W-1 T4CKR0 bit 0
Unimplemented: Read as `0' T5CKR5:T5CKR0: Assign Timer5 External Clock (T5CK) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' T4CKR5:T4CKR0: Assign Timer4 External Clock (T4CK) to Corresponding RPn or RPIn Pin bits
REGISTER 9-6:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0
RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7
U-0 -- R/W-1 IC2R5 R/W-1 IC2R4 R/W-1 IC2R3 R/W-1 IC2R2 R/W-1 IC2R1 R/W-1 IC2R0 bit 8 U-0 -- R/W-1 IC1R5 R/W-1 IC1R4 R/W-1 IC1R3 R/W-1 IC1R2 R/W-1 IC1R1 R/W-1 IC1R0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' IC2R5:IC2R0: Assign Input Capture 2 (IC2) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' IC1R5:IC1R0: Assign Input Capture 1 (IC1) to Corresponding RPn or RPIn Pin bits
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REGISTER 9-7:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 IC3R5 R/W-1 IC3R4 R/W-1 IC3R3 R/W-1 IC3R2 R/W-1 IC3R1
RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8
U-0 -- R/W-1 IC4R5 R/W-1 IC4R4 R/W-1 IC4R3 R/W-1 IC4R2 R/W-1 IC4R1 R/W-1 IC4R0 bit 8 R/W-1 IC3R0 bit 0
Unimplemented: Read as `0' IC4R5:IC4R0: Assign Input Capture 4 (IC4) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' IC3R5:IC3R0: Assign Input Capture 3 (IC3) to Corresponding RPn or RPIn Pin bits
REGISTER 9-8:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0
RPINR9: PERIPHERAL PIN SELECT INPUT REGISTER 9
U-0 -- R/W-1 IC6R5 R/W-1 IC6R4 R/W-1 IC6R3 R/W-1 IC6R2 R/W-1 IC6R1 R/W-1 IC6R0 bit 8 U-0 -- R/W-1 IC5R5 R/W-1 IC5R4 R/W-1 IC5R3 R/W-1 IC5R2 R/W-1 IC5R1 R/W-1 IC5R0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' IC6R5:IC6R0: Assign Input Capture 6 (IC6) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' IC5R5:IC5R0: Assign Input Capture 5 (IC5) to Corresponding RPn or RPIn Pin bits
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REGISTER 9-9:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 IC7R5 R/W-1 IC7R4 R/W-1 IC7R3 R/W-1 IC7R2 R/W-1 IC7R1
RPINR10: PERIPHERAL PIN SELECT INPUT REGISTER 10
U-0 -- R/W-1 IC8R5 R/W-1 IC8R4 R/W-1 IC8R3 R/W-1 IC8R2 R/W-1 IC8R1 R/W-1 IC8R0 bit 8 R/W-1 IC7R0 bit 0
Unimplemented: Read as `0' IC8R5:IC8R0: Assign Input Capture 8 (IC8) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' IC7R5:IC7R0: Assign Input Capture 7 (IC7) to Corresponding RPn or RPIn Pin bits
REGISTER 9-10:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0
RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11
U-0 -- R/W-1 OCFBR5 R/W-1 OCFBR4 R/W-1 OCFBR3 R/W-1 OCFBR2 R/W-1 OCFBR1 R/W-1 OCFBR0 bit 8 U-0 -- R/W-1 OCFAR5 R/W-1 OCFAR4 R/W-1 OCFAR3 R/W-1 OCFAR2 R/W-1 OCFAR1 R/W-1 OCFAR0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' OCFBR5:OCFBR0: Assign Output Compare Fault B (OCFB) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' OCFAR5:OCFAR0: Assign Output Compare Fault A (OCFA) to Corresponding RPn or RPIn Pin bits
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REGISTER 9-11:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
RPINR15: PERIPHERAL PIN SELECT INPUT REGISTER 15
U-0 -- R/W-1 IC9R5 R/W-1 IC9R4 R/W-1 IC9R3 R/W-1 IC9R2 R/W-1 IC9R1 R/W-1 IC9R0 bit 8
Unimplemented: Read as `0' IC9R5:IC9R0: Assign Input Capture 9 (IC9) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0'
REGISTER 9-12:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-0
RPINR17: PERIPHERAL PIN SELECT INPUT REGISTER 17
U-0 -- R/W-1 U3RXR5 R/W-1 U3RXR4 R/W-1 U3RXR3 R/W-1 U3RXR2 R/W-1 U3RXR1 R/W-1 U3RXR0 bit 8 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' U3RXR5:U3RXR0: Assign UART3 Receive (U3RX) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0'
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REGISTER 9-13:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 U1RXR5 R/W-1 U1RXR4 R/W-1 U1RXR3 R/W-1 U1RXR2 R/W-1 U1RXR1
RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18
U-0 -- R/W-1 U1CTSR5 R/W-1 U1CTSR4 R/W-1 U1CTSR3 R/W-1 U1CTSR2 R/W-1 U1CTSR1 R/W-1 U1CTSR0 bit 8 R/W-1 U1RXR0 bit 0
Unimplemented: Read as `0' U1CTSR5:U1CTSR0: Assign UART1 Clear to Send (U1CTS) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' U1RXR5:U1RXR0: Assign UART1 Receive (U1RX) to Corresponding RPn or RPIn Pin bits
REGISTER 9-14:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0
RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19
U-0 -- R/W-1 U2CTSR5 R/W-1 U2CTSR4 R/W-1 U2CTSR3 R/W-1 U2CTSR2 R/W-1 U2CTSR1 R/W-1 U2CTSR0 bit 8 U-0 -- R/W-1 U2RXR5 R/W-1 U2RXR4 R/W-1 U2RXR3 R/W-1 U2RXR2 R/W-1 U2RXR1 R/W-1 U2RXR0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' U2CTSR5:U2CTSR0: Assign UART2 Clear to Send (U2CTS) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' U2RXR5:U2RXR0: Assign UART2 Receive (U2RX) to Corresponding RPn or RPIn Pin bits
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REGISTER 9-15:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 SDI1R5 R/W-1 SDI1R4 R/W-1 SDI1R3 R/W-1 SDI1R2 R/W-1 SDI1R1
RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20
U-0 -- R/W-1 SCK1R5 R/W-1 SCK1R4 R/W-1 SCK1R3 R/W-1 SCK1R2 R/W-1 SCK1R1 R/W-1 SCK1R0 bit 8 R/W-1 SDI1R0 bit 0
Unimplemented: Read as `0' SCK1R5:SCK1R0: Assign SPI1 Clock Input (SCK1IN) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' SDI1R5:SDI1R0: Assign SPI1 Data Input (SDI1) to Corresponding RPn or RPIn Pin bits
REGISTER 9-16:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0
RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21
U-0 -- R/W-1 U3CTSR5 R/W-1 U3CTSR4 R/W-1 U3CTSR3 R/W-1 U3CTSR2 R/W-1 U3CTSR1 R/W-1 U3CTSR0 bit 8 U-0 -- R/W-1 SS1R5 R/W-1 SS1R4 R/W-1 SS1R3 R/W-1 SS1R2 R/W-1 SS1R1 R/W-1 SS1R0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' U3CTSR5:U3CTSR0: Assign UART3 Clear to Send (U3CTS) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' SS1R5:SS1R0: Assign SPI1 Slave Select Input (SS1IN) to Corresponding RPn or RPIn Pin bits
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REGISTER 9-17:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 SDI2R5 R/W-1 SDI2R4 R/W-1 SDI2R3 R/W-1 SDI2R2 R/W-1 SDI2R1
RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22
U-0 -- R/W-1 SCK2R5 R/W-1 SCK2R4 R/W-1 SCK2R3 R/W-1 SCK2R2 R/W-1 SCK2R1 R/W-1 SCK2R0 bit 8 R/W-1 SDI2R0 bit 0
Unimplemented: Read as `0' SCK2R5:SCK2R0: Assign SPI2 Clock Input (SCK2IN) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' SDI2R5:SDI2R0: Assign SPI2 Data Input (SDI2) to Corresponding RPn or RPIn Pin bits
REGISTER 9-18:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-6 bit 5-0
RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- R/W-1 SS2R5 R/W-1 SS2R4 R/W-1 SS2R3 R/W-1 SS2R2 R/W-1 SS2R1 R/W-1 SS2R0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' SS2R5:SS2R0: Assign SPI2 Slave Select Input (SS2IN) to Corresponding RPn or RPIn Pin bits
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REGISTER 9-19:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 U4RXR5 R/W-1 U4RXR4 R/W-1 U4RXR3 R/W-1 U4RXR2 R/W-1 U4RXR1
RPINR27: PERIPHERAL PIN SELECT INPUT REGISTER 27
U-0 -- R/W-1 U4CTSR5 R/W-1 U4CTSR4 R/W-1 U4CTSR3 R/W-1 U4CTSR2 R/W-1 U4CTSR1 R/W-1 U4CTSR0 bit 8 R/W-1 U4RXR0 bit 0
Unimplemented: Read as `0' U4CTSR5:U4CTSR0: Assign UART4 Clear to Send (U4CTS) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' U4RXR5:U4RXR0: Assign UART4 Receive (U4RX) to Corresponding RPn or RPIn Pin bits
REGISTER 9-20:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0
RPINR28: PERIPHERAL PIN SELECT INPUT REGISTER 28
U-0 -- R/W-1 SCK3R5 R/W-1 SCK3R4 R/W-1 SCK3R3 R/W-1 SCK3R2 R/W-1 SCK3R1 R/W-1 SCK3R0 bit 8 U-0 -- R/W-1 SDI3R5 R/W-1 SDI3R4 R/W-1 SDI3R3 R/W-1 SDI3R2 R/W-1 SDI3R1 R/W-1 SDI3R0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' SCK3R5:SCK3R0: Assign SPI3 Clock Input (SCK3IN) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' SDI3R5:SDI3R0: Assign SPI3 Data Input (SDI3) to Corresponding RPn or RPIn Pin bits
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REGISTER 9-21:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 SS3R5 R/W-1 SS3R4 R/W-1 SS3R3 R/W-1 SS3R2 R/W-1 SS3R1
RPINR29: PERIPHERAL PIN SELECT INPUT REGISTER 29
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-1 SS3R0 bit 0
Unimplemented: Read as `0' SS3R5:SS3R0: Assign SPI3 Slave Select Input (SS31IN) to Corresponding RPn or RPIn Pin bits
REGISTER 9-22:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0
RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0
U-0 -- R/W-0 RP1R5 R/W-0 RP1R4 R/W-0 RP1R3 R/W-0 RP1R2 R/W-0 RP1R1 R/W-0 RP1R0 bit 8 U-0 -- R/W-0 RP0R5 R/W-0 RP0R4 R/W-0 RP0R3 R/W-0 RP0R2 R/W-0 RP0R1 R/W-0 RP0R0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' RP1R5:RP1R0: RP1 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP1 (see Table 9-2 for peripheral function numbers) Unimplemented: Read as `0' RP0R5:RP0R0: RP0 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP0 (see Table 9-2 for peripheral function numbers)
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REGISTER 9-23:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 RP2R5 R/W-0 RP2R4 R/W-0 RP2R3 R/W-0 RP2R2 R/W-0 RP2R1
RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1
U-0 -- R/W-0 RP3R5 R/W-0 RP3R4 R/W-0 RP3R3 R/W-0 RP3R2 R/W-0 RP3R1 R/W-0 RP3R0 bit 8 R/W-0 RP2R0 bit 0
Unimplemented: Read as `0' RP3R5:RP3R0: RP3 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP3 (see Table 9-2 for peripheral function numbers) Unimplemented: Read as `0' RP2R5:RP2R0: RP2 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP2 (see Table 9-2 for peripheral function numbers)
REGISTER 9-24:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0
RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2
U-0 -- R/W-0 RP5R5(1) R/W-0 RP5R4(1) R/W-0 RP5R3(1) R/W-0 RP5R2(1) R/W-0 RP5R1(1) R/W-0 RP5R0(1) bit 8 U-0 -- R/W-0 RP4R5 R/W-0 RP4R4 R/W-0 RP4R3 R/W-0 RP4R2 R/W-0 RP4R1 R/W-0 RP4R0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' RP5R5:RP5R0: RP5 Output Pin Mapping bits(1) Peripheral Output number n is assigned to pin RP5 (see Table 9-2 for peripheral function numbers) Unimplemented: Read as `0' RP4R5:RP4R0: RP4 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP4 (see Table 9-2 for peripheral function numbers) Unimplemented in 64-pin devices; read as `0'.
Note 1:
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REGISTER 9-25:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 RP6R5 R/W-0 RP6R4 R/W-0 RP6R3 R/W-0 RP6R2 R/W-0 RP6R1
RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3
U-0 -- R/W-0 RP7R5 R/W-0 RP7R4 R/W-0 RP7R3 R/W-0 RP7R2 R/W-0 RP7R1 R/W-0 RP7R0 bit 8 R/W-0 RP6R0 bit 0
Unimplemented: Read as `0' RP7R5:RP7R0: RP7 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP7 (see Table 9-2 for peripheral function numbers) Unimplemented: Read as `0' RP6R5:RP6R0: RP6 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP6 (see Table 9-2 for peripheral function numbers)
REGISTER 9-26:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0
RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4
U-0 -- R/W-0 RP9R5 R/W-0 RP9R4 R/W-0 RP9R3 R/W-0 RP9R2 R/W-0 RP9R1 R/W-0 RP9R0 bit 8 U-0 -- R/W-0 RP8R5 R/W-0 RP8R4 R/W-0 RP8R3 R/W-0 RP8R2 R/W-0 RP8R1 R/W-0 RP8R0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' RP9R5:RP9R0: RP9 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP9 (see Table 9-2 for peripheral function numbers) Unimplemented: Read as `0' RP8R5:RP8R0: RP8 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP8 (see Table 9-2 for peripheral function numbers)
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REGISTER 9-27:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 RP10R5 R/W-0 RP10R4 R/W-0 RP10R3 R/W-0 RP10R2 R/W-0 RP10R1
RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5
U-0 -- R/W-0 RP11R5 R/W-0 RP11R4 R/W-0 RP11R3 R/W-0 RP11R2 R/W-0 RP11R1 R/W-0 RP11R0 bit 8 R/W-0 RP10R0 bit 0
Unimplemented: Read as `0' RP11R5:RP11R0: RP11 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP11 (see Table 9-2 for peripheral function numbers) Unimplemented: Read as `0' RP10R5:RP10R0: RP10 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP10 (see Table 9-2 for peripheral function numbers)
REGISTER 9-28:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0
RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6
U-0 -- R/W-0 RP13R5 R/W-0 RP13R4 R/W-0 RP13R3 R/W-0 RP13R2 R/W-0 RP13R1 R/W-0 RP13R0 bit 8 U-0 -- R/W-0 RP12R5 R/W-0 RP12R4 R/W-0 RP12R3 R/W-0 RP12R2 R/W-0 RP12R1 R/W-0 RP12R0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' RP13R5:RP13R0: RP13 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP13 (see Table 9-2 for peripheral function numbers) Unimplemented: Read as `0' RP12R5:RP12R0: RP12 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP12 (see Table 9-2 for peripheral function numbers)
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REGISTER 9-29:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 RP14R5 R/W-0 RP14R4 R/W-0 RP14R3 R/W-0 RP14R2 R/W-0 RP14R1
RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7
U-0 -- R/W-0 RP15R5(1) R/W-0 RP15R4(1) R/W-0 RP15R3(1) R/W-0 RP15R2(1) R/W-0 RP15R1(1) R/W-0 RP15R0(1) bit 8 R/W-0 RP14R0 bit 0
Unimplemented: Read as `0' RP15R5:RP15R0: RP15 Output Pin Mapping bits(1) Peripheral Output number n is assigned to pin RP0 (see Table 9-2 for peripheral function numbers) Unimplemented: Read as `0' RP14R5:RP14R0: RP14 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP14 (see Table 9-2 for peripheral function numbers) Unimplemented in 64-pin devices; read as `0'.
Note 1:
REGISTER 9-30:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0
RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8
U-0 -- R/W-0 RP17R5 R/W-0 RP17R4 R/W-0 RP17R3 R/W-0 RP17R2 R/W-0 RP17R1 R/W-0 RP17R0 bit 8 U-0 -- R/W-0 RP16R5 R/W-0 RP16R4 R/W-0 RP16R3 R/W-0 RP16R2 R/W-0 RP16R1 R/W-0 RP16R0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' RP17R5:RP17R0: RP17 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP17 (see Table 9-2 for peripheral function numbers) Unimplemented: Read as `0' RP16R5:RP16R0: RP16 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP16 (see Table 9-2 for peripheral function numbers)
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REGISTER 9-31:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 RP18R5 R/W-0 RP18R4 R/W-0 RP18R3 R/W-0 RP18R2 R/W-0 RP18R1
RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9
U-0 -- R/W-0 RP19R5 R/W-0 RP19R4 R/W-0 RP19R3 R/W-0 RP19R2 R/W-0 RP19R1 R/W-0 RP19R0 bit 8 R/W-0 RP18R0 bit 0
Unimplemented: Read as `0' RP19R5:RP19R0: RP19 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP19 (see Table 9-2 for peripheral function numbers) Unimplemented: Read as `0' RP18R5:RP18R0: RP18 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP18 (see Table 9-2 for peripheral function numbers)
REGISTER 9-32:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0
RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10
U-0 -- R/W-0 RP21R5 R/W-0 RP21R4 R/W-0 RP21R3 R/W-0 RP21R2 R/W-0 RP21R1 R/W-0 RP21R0 bit 8 U-0 -- R/W-0 RP20R5 R/W-0 RP20R4 R/W-0 RP20R3 R/W-0 RP20R2 R/W-0 RP20R1 R/W-0 RP20R0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' RP21R5:RP21R0: RP21 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP21 (see Table 9-2 for peripheral function numbers) Unimplemented: Read as `0' RP20R5:RP20R0: RP20 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP20 (see Table 9-2 for peripheral function numbers)
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REGISTER 9-33:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 RP22R5 R/W-0 RP22R4 R/W-0 RP22R3 R/W-0 RP22R2 R/W-0 RP22R1
RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11
U-0 -- R/W-0 RP23R5 R/W-0 RP23R4 R/W-0 RP23R3 R/W-0 RP23R2 R/W-0 RP23R1 R/W-0 RP23R0 bit 8 R/W-0 RP22R0 bit 0
Unimplemented: Read as `0' RP23R5:RP23R0: RP23 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP23 (see Table 9-2 for peripheral function numbers) Unimplemented: Read as `0' RP22R5:RP22R0: RP22 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP22 (see Table 9-2 for peripheral function numbers)
REGISTER 9-34:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0
RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12
U-0 -- R/W-0 RP25R5 R/W-0 RP25R4 R/W-0 RP25R3 R/W-0 RP25R2 R/W-0 RP25R1 R/W-0 RP25R0 bit 8 U-0 -- R/W-0 RP24R5 R/W-0 RP24R4 R/W-0 RP24R3 R/W-0 RP24R2 R/W-0 RP24R1 R/W-0 RP24R0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' RP25R5:RP25R0: RP25 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP25 (see Table 9-2 for peripheral function numbers) Unimplemented: Read as `0' RP24R5:RP24R0: RP24 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP24 (see Table 9-2 for peripheral function numbers)
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REGISTER 9-35:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 RP26R5 R/W-0 RP26R4 R/W-0 RP26R3 R/W-0 RP26R2 R/W-0 RP26R1
RPOR13: PERIPHERAL PIN SELECT OUTPUT REGISTER 13
U-0 -- R/W-0 RP27R5 R/W-0 RP27R4 R/W-0 RP27R3 R/W-0 RP27R2 R/W-0 RP27R1 R/W-0 RP27R0 bit 8 R/W-0 RP26R0 bit 0
Unimplemented: Read as `0' RP27R5:RP27R0: RP27 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP27 (see Table 9-2 for peripheral function numbers) Unimplemented: Read as `0' RP26R5:RP26R0: RP26 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP26 (see Table 9-2 for peripheral function numbers)
REGISTER 9-36:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0
RPOR14: PERIPHERAL PIN SELECT OUTPUT REGISTER 14
U-0 -- R/W-0 RP29R5 R/W-0 RP29R4 R/W-0 RP29R3 R/W-0 RP29R2 R/W-0 RP29R1 R/W-0 RP29R0 bit 8 U-0 -- R/W-0 RP28R5 R/W-0 RP28R4 R/W-0 RP28R3 R/W-0 RP28R2 R/W-0 RP28R1 R/W-0 RP28R0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' RP29R5:RP29R0: RP29 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP29 (see Table 9-2 for peripheral function numbers) Unimplemented: Read as `0' RP28R5:RP28R0: RP28 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP28 (see Table 9-2 for peripheral function numbers)
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REGISTER 9-37:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 RP30R5(2) R/W-0 RP30R4(2) R/W-0 RP30R3(2) R/W-0 RP30R2(2) R/W-0 RP30R1(2)
RPOR15: PERIPHERAL PIN SELECT OUTPUT REGISTER 15
U-0 -- R/W-0 RP31R5
(1)
R/W-0 RP31R4
(1)
R/W-0 RP31R3
(1)
R/W-0 RP31R2
(1)
R/W-0 RP31R1
(1)
R/W-0 RP31R0(1) bit 8 R/W-0 RP30R0(2) bit 0
Unimplemented: Read as `0' RP31R5:RP31R0: RP31 Output Pin Mapping bits(1) Peripheral Output number n is assigned to pin RP31 (see Table 9-2 for peripheral function numbers) Unimplemented: Read as `0' RP30R5:RP30R0: RP30 Output Pin Mapping bits(2) Peripheral Output number n is assigned to pin RP30 (see Table 9-2 for peripheral function numbers) Unimplemented in 64-pin and 80-pin devices; read as `0'. Unimplemented in 64-pin devices; read as `0'.
Note 1: 2:
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10.0
Note:
TIMER1
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 14. Timers" (DS39704).
Figure 10-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. 2. 3. 4. 5. 6. Set the TON bit (= 1). Select the timer prescaler ratio using the TCKPS1:TCKPS0 bits. Set the Clock and Gating modes using the TCS and TGATE bits. Set or clear the TSYNC bit to configure synchronous or asynchronous operation. Load the timer period value into the PR1 register. If interrupts are required, set the interrupt enable bit, T1IE. Use the priority bits, T1IP2:T1IP0, to set the interrupt priority.
The Timer1 module is a 16-bit timer which can serve as the time counter for the Real-Time Clock (RTC), or operate as a free-running, interval timer/counter. Timer1 can operate in three modes: * 16-Bit Timer * 16-Bit Synchronous Counter * 16-Bit Asynchronous Counter Timer1 also supports these features: * Timer Gate Operation * Selectable Prescaler Settings * Timer Operation during CPU Idle and Sleep modes * Interrupt on 16-Bit Period Register Match or Falling Edge of External Gate Signal
FIGURE 10-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM
TCKPS1:TCKPS0
SOSCO/ T1CK SOSCEN SOSCI Gate Sync TCY TGATE
1x 01 00
TON
2 Prescaler 1, 8, 64, 256
TGATE TCS Q Q Reset D CK 0 TMR1 1 Comparator TSYNC Sync
Set T1IF
1 0
Equal
PR1
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REGISTER 10-1:
R/W-0 TON bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 TGATE R/W-0 TCKPS1 R/W-0 TCKPS0 U-0 -- R/W-0 TSYNC R/W-0 TCS U-0 -- bit 0
T1CON: TIMER1 CONTROL REGISTER(1)
U-0 -- R/W-0 TSIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8
TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 Unimplemented: Read as `0' TSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' TGATE: Timer1 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled TCKPS1:TCKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 Unimplemented: Read as `0' TSYNC: Timer1 External Clock Input Synchronization Select bit When TCS = 1: 1 = Synchronize external clock input 0 = Do not synchronize external clock input When TCS = 0: This bit is ignored. TCS: Timer1 Clock Source Select bit 1 = External clock from T1CK pin (on the rising edge) 0 = Internal clock (FOSC/2) Unimplemented: Read as `0' Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended.
bit 14 bit 13
bit 12-7 bit 6
bit 5-4
bit 3 bit 2
bit 1
bit 0 Note 1:
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11.0
Note:
TIMER2/3 AND TIMER4/5
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 14. Timers" (DS39704).
To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. 2. 3. Set the T32 bit (T2CON<3> or T4CON<3> = 1). Select the prescaler ratio for Timer2 or Timer4 using the TCKPS1:TCKPS0 bits. Set the Clock and Gating modes using the TCS and TGATE bits. If TCS is set to external clock, RPINRx (TxCK) must be configured to an available RPn pin. See Section 9.4 "Peripheral Pin Select" for more information. Load the timer period value. PR3 (or PR5) will contain the most significant word of the value while PR2 (or PR4) contains the least significant word. If interrupts are required, set the interrupt enable bit, T3IE or T5IE; use the priority bits, T3IP2:T3IP0 or T5IP2:T5IP0, to set the interrupt priority. Note that while Timer2 or Timer4 controls the timer, the interrupt appears as a Timer3 or Timer5 interrupt. Set the TON bit (= 1).
The Timer2/3 and Timer4/5 modules are 32-bit timers, which can also be configured as four independent 16-bit timers with selectable operating modes. As 32-bit timers, Timer2/3 and Timer4/5 can each operate in three modes: * Two independent 16-bit timers with all 16-bit operating modes (except Asynchronous Counter mode) * Single 32-bit timer * Single 32-bit synchronous counter They also support these features: * * * * * Timer Gate Operation Selectable Prescaler Settings Timer Operation during Idle and Sleep modes Interrupt on a 32-Bit Period Register Match ADC Event Trigger (Timer4/5 only)
4.
5.
6.
The timer value, at any point, is stored in the register pair, TMR3:TMR2 (or TMR5:TMR4). TMR3 (TMR5) always contains the most significant word of the count, while TMR2 (TMR4) contains the least significant word. To configure any of the timers for individual 16-bit operation: 1. Clear the T32 bit corresponding to that timer (T2CON<3> for Timer2 and Timer3 or T4CON<3> for Timer4 and Timer5). Select the timer prescaler ratio using the TCKPS1:TCKPS0 bits. Set the Clock and Gating modes using the TCS and TGATE bits. See Section 9.4 "Peripheral Pin Select" for more information. Load the timer period value into the PRx register. If interrupts are required, set the interrupt enable bit, TxIE; use the priority bits, TxIP2:TxIP0, to set the interrupt priority. Set the TON bit (TxCON<15> = 1).
Individually, all four of the 16-bit timers can function as synchronous timers or counters. They also offer the features listed above, except for the ADC Event Trigger; this is implemented only with Timer5. The operating modes and enabled features are determined by setting the appropriate bit(s) in the T2CON, T3CON, T4CON and T5CON registers. T2CON and T4CON are shown in generic form in Register 11-1; T3CON and T5CON are shown in Register 11-2. For 32-bit timer/counter operation, Timer2 and Timer4 are the least significant word; Timer3 and Timer4 are the most significant word of the 32-bit timers. Note: For 32-bit operation, T3CON and T5CON control bits are ignored. Only T2CON and T4CON control bits are used for setup and control. Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags.
2. 3.
4. 5.
6.
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FIGURE 11-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM
TCKPS1:TCKPS0 2 Prescaler 1, 8, 64, 256
T2CK (T4CK) Gate Sync TCY TGATE
1x 01 00
TON
TGATE(2) TCS(2)
Set T3IF (T5IF)
1 0 PR3 (PR5)
Q Q
D CK PR2 (PR4)
ADC Event Trigger(3)
Equal MSB Reset 16
Comparator LSB TMR3 (TMR5) TMR2 (TMR4) Sync
Read TMR2 (TMR4)
(1)
Write TMR2 (TMR4)(1)
16 TMR3HLD (TMR5HLD) 16
Data Bus<15:0>
Note 1: 2: 3:
The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON and T4CON registers. The timer clock input must be assigned to an available RPn pin before use. Please see Section 9.4 "Peripheral Pin Select" for more information. The ADC Event Trigger is available only on Timer 2/3 in 32-bit mode and Timer 3 in 16-bit mode.
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FIGURE 11-2: TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM
TCKPS1:TCKPS0 2 Prescaler 1, 8, 64, 256
T2CK (T4CK) Gate Sync TGATE TCY 1 Set T2IF (T4IF) 0 Reset Q Q D CK
1x 01 00
TON
TCS(1) TGATE(1)
TMR2 (TMR4)
Sync
Equal
Comparator
PR2 (PR4) Note 1: The timer clock input must be assigned to an available RPn pin before use. Please see Section 9.4 "Peripheral Pin Select" for more information.
FIGURE 11-3:
TIMER3 AND TIMER5 (16-BIT ASYNCHRONOUS) BLOCK DIAGRAM
TON TCKPS1:TCKPS0 2 Prescaler 1, 8, 64, 256
T3CK (T5CK)
Sync
1x 01
TGATE TCY 1 Set T3IF (T5IF) 0 Reset Q Q D CK
00 TCS(1) TGATE(1)
TMR3 (TMR5)
ADC Event Trigger(2) Equal
Comparator
PR3 (PR5)
Note 1: 2:
The timer clock input must be assigned to an available RPn pin before use. Please see Section 9.4 "Peripheral Pin Select" for more information. The ADC Event Trigger is available only on Timer3.
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REGISTER 11-1:
R/W-0 TON bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 TGATE R/W-0 TCKPS1 R/W-0 TCKPS0 R/W-0 T32(1) U-0 -- R/W-0 TCS(2) U-0 -- bit 0
TxCON: TIMER2 AND TIMER4 CONTROL REGISTER(3)
U-0 -- R/W-0 TSIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8
TON: Timerx On bit When TxCON<3> = 1: 1 = Starts 32-bit Timerx/y 0 = Stops 32-bit Timerx/y When TxCON<3> = 0: 1 = Starts 16-bit Timerx 0 = Stops 16-bit Timerx Unimplemented: Read as `0' TSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' TGATE: Timerx Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled TCKPS1:TCKPS0: Timerx Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 T32: 32-Bit Timer Mode Select bit(1) 1 = Timerx and Timery form a single 32-bit timer 0 = Timerx and Timery act as two 16-bit timers In 32-bit mode, T3CON control bits do not affect 32-bit timer operation. Unimplemented: Read as `0' TCS: Timerx Clock Source Select bit(2) 1 = External clock from pin, TxCK (on the rising edge) 0 = Internal clock (FOSC/2) Unimplemented: Read as `0' In 32-bit mode, the T3CON or T5CON control bits do not affect 32-bit timer operation. If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. For more information, see Section 9.4 "Peripheral Pin Select". Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended.
bit 14 bit 13
bit 12-7 bit 6
bit 5-4
bit 3
bit 2 bit 1
bit 0 Note 1: 2: 3:
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REGISTER 11-2:
R/W-0 TON(1) bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 TGATE(1) R/W-0 TCKPS1(1) R/W-0 TCKPS0(1) U-0 -- U-0 -- R/W-0 TCS(1,2) U-0 -- bit 0
TyCON: TIMER3 AND TIMER5 CONTROL REGISTER(3)
U-0 -- R/W-0 TSIDL(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8
TON: Timery On bit(1) 1 = Starts 16-bit Timery 0 = Stops 16-bit Timery Unimplemented: Read as `0' TSIDL: Stop in Idle Mode bit(1) 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' TGATE: Timery Gated Time Accumulation Enable bit(1) When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled TCKPS1:TCKPS0: Timery Input Clock Prescale Select bits(1) 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 Unimplemented: Read as `0' TCS: Timery Clock Source Select bit(1,2) 1 = External clock from pin TyCK (on the rising edge) 0 = Internal clock (FOSC/2) Unimplemented: Read as `0' When 32-bit operation is enabled (T2CON<3> or T4CON<3> = 1), these bits have no effect on Timery operation; all timer functions are set through T2CON and T4CON. If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. See Section 9.4 "Peripheral Pin Select" for more information. Changing the value of TyCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended.
bit 14 bit 13
bit 12-7 bit 6
bit 5-4
bit 3-2 bit 1
bit 0 Note 1: 2: 3:
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NOTES:
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12.0
Note:
INPUT CAPTURE WITH DEDICATED TIMERS
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", Section 34. "Input Capture with Dedicated Timer" (DS39722).
12.1
12.1.1
General Operating Modes
SYNCHRONOUS AND TRIGGER MODES
Devices in the PIC24FJ256GB110 family all feature 9 independent input capture modules. Each of the modules offers a wide range of configuration and operating options for capturing external pulse events and generating interrupts. Key features of the input capture module include: * Hardware-configurable for 32-bit operation in all modes by cascading two adjacent modules * Synchronous and Trigger modes of output compare operation, with up to 30 user-selectable trigger/sync sources available * A 4-level FIFO buffer for capturing and holding timer values for several events * Configurable interrupt generation * Up to 6 clock sources available for each module, driving a separate internal 16-bit counter The module is controlled through two registers, ICxCON1 (Register 12-1) and ICxCON2 (Register 12-2). A general block diagram of the module is shown in Figure 12-1.
By default, the input capture module operates in a free-running mode. The internal 16-bit counter ICxTMR counts up continuously, wrapping around from FFFFh to 0000h on each overflow, with its period synchronized to the selected external clock source. When a capture event occurs, the current 16-bit value of the internal counter is written to the FIFO buffer. In Synchronous mode, the module begins capturing events on the ICx pin as soon as its selected clock source is enabled. Whenever an event occurs on the selected sync source, the internal counter is reset. In Trigger mode, the module waits for a Sync event from another internal module to occur before allowing the internal counter to run. Standard, free-running operation is selected by setting the SYNCSEL bits to `00000', and clearing the ICTRIG bit (ICxCON2<7>). Synchronous and Trigger modes are selected any time the SYNCSEL bits are set to any value except `00000'. The ICTRIG bit selects either Synchronous or Trigger mode; setting the bit selects Trigger mode operation. In both modes, the SYNCSEL bits determine the sync/trigger source. When the SYNCSEL bits are set to `00000' and ICTRIG is set, the module operates in Software Trigger mode. In this case, capture operations are started by manually setting the TRIGSTAT bit (ICxCON2<6>).
FIGURE 12-1:
INPUT CAPTURE BLOCK DIAGRAM
ICM2:ICM0 ICI1:ICI0
ICx Pin(1)
Prescaler Counter 1:1/4/16
Edge Detect Logic and Clock Synchronizer
Event and Interrupt Logic
Set ICxIF
ICTSEL2:ICTSEL0
IC Clock Sources
Clock Select
Increment
16 ICxTMR 4-Level FIFO Buffer 16
Trigger and Sync Logic Trigger and Sync Sources
Reset
16 ICxBUF
SYNCSEL4:SYNCSEL0 TRIGGER ICOV, ICBNE
System Bus
Note 1:
The ICx inputs must be assigned to an available RPn pin before use. Please see Section 9.4 "Peripheral Pin Select" for more information.
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12.1.2 CASCADED (32-BIT) MODE
By default, each module operates independently with its own 16-bit timer. To increase resolution, adjacent even and odd modules can be configured to function as a single 32-bit module. (For example, modules 1 and 2 are paired, as are modules 3 and 4, and so on.) The odd-numbered module (ICx) provides the Least Significant 16 bits of the 32-bit register pairs, and the even module (ICy) provides the Most Significant 16 bits. Wraparounds of the ICx registers cause an increment of their corresponding ICy registers. Cascaded operation is configured in hardware by setting the IC32 bits (ICxCON2<8>) for both modules. For 32-bit cascaded operations, the setup procedure is slightly different: 1. Set the IC32 bits for both modules (ICyCON2<8> and (ICxCON2<8>), enabling the even-numbered module first. This ensures the modules will start functioning in unison. Set the ICTSEL and SYNCSEL bits for both modules to select the same sync/trigger and time base source. Set the even module first, then the odd module. Both modules must use the same ICTSEL and SYNCSEL settings. Clear the ICTRIG bit of the even module (ICyCON2<7>); this forces the module to run in Synchronous mode with the odd module, regardless of its trigger setting. Use the odd module's ICI bits (ICxCON1<6:5>) to the desired interrupt frequency. Use the ICTRIG bit of the odd module (ICxCON2<7>) to configure Trigger or Synchronous mode operation. Note: For Synchronous mode operation, enable the sync source as the last step. Both input capture modules are held in Reset until the sync source is enabled.
2.
3.
12.2
Capture Operations
4. 5.
The input capture module can be configured to capture timer values and generate interrupts on rising edges on ICx, or all transitions on ICx. Captures can be configured to occur on all rising edges, or just some (every 4th or 16th). Interrupts can be independently configured to generate on each event, or a subset of events. To set up the module for capture operations: 1. 2. 3. Configure the ICx input for one of the available peripheral pin select pins. If Synchronous mode is to be used, disable the sync source before proceeding. Make sure that any previous data has been removed from the FIFO by reading ICxBUF until the ICBNE bit (ICxCON1<3>) is cleared. Set the SYNCSEL bits (ICxCON2<4:0>) to the desired sync/trigger source. Set the ICTSEL bits (ICxCON1<12:10>) for the desired clock source. Set the ICI bits (ICxCON1<6:5>) to the desired interrupt frequency Select Synchronous or Trigger mode operation: a) Check that the SYNCSEL bits are not set to `00000'. b) For Synchronous mode, clear the ICTRIG bit (ICxCON2<7>). c) For Trigger mode, set ICTRIG, and clear the TRIGSTAT bit (ICxCON2<6>). Set the ICM bits (ICxCON1<2:0>) to the desired operational mode. Enable the selected trigger/sync source.
6.
Use the ICM bits of the odd module (ICxCON1<2:0>) to set the desired capture mode.
4. 5. 6. 7.
The module is ready to capture events when the time base and the trigger/sync source are enabled. When the ICBNE bit (ICxCON1<3>) becomes set, at least one capture value is available in the FIFO. Read input capture values from the FIFO until the ICBNE clears to `0'. For 32-bit operation, read both the ICxBUF and ICyBUF for the full 32-bit timer value (ICxBUF for the lsw, ICyBUF for the msw). At least one capture value is available in the FIFO buffer when the odd module's ICBNE bit (ICxCON1<3>) becomes set. Continue to read the buffer registers until ICBNE is cleared (perform automatically by hardware).
8. 9.
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REGISTER 12-1:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 W = Writable bit `1' = Bit is set HC = Hardware Clearable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 ICI1 R/W-0 ICI0 R-0, HC ICOV R-0, HC ICBNE R/W-0 ICM2(1) R/W-0 ICM1(1)
ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1
U-0 -- R/W-0 ICSIDL R/W-0 ICTSEL2 R/W-0 ICTSEL1 R/W-0 ICTSEL0 U-0 -- U-0 -- bit 8 R/W-0 ICM0(1) bit 0
Unimplemented: Read as `0' ICSIDL: Input Capture x Module Stop in Idle Control bit 1 = Input capture module halts in CPU Idle mode 0 = Input capture module continues to operate in CPU Idle mode ICTSEL2:ICTSEL0: Input Capture Timer Select bits 111 = System clock (FOSC/2) 110 = Reserved 101 = Reserved 100 = Timer1 011 = Timer5 010 = Timer4 001 = Timer2 000 = Timer3 Unimplemented: Read as `0' ICI1:ICI0: Select Number of Captures per Interrupt bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event ICOV: Input Capture x Overflow Status Flag bit (read-only) 1 = Input capture overflow occurred 0 = No input capture overflow occurred ICBNE: Input Capture x Buffer Empty Status bit (read-only) 1 = Input capture buffer is not empty, at least one more capture value can be read 0 = Input capture buffer is empty ICM2:ICM0: Input Capture Mode Select bits(1) 111 = Interrupt mode: input capture functions as interrupt pin only when device is in Sleep or Idle mode (rising edge detect only, all other control bits are not applicable) 110 = Unused (module disabled) 101 = Prescaler Capture mode: capture on every 16th rising edge 100 = Prescaler Capture mode: capture on every 4th rising edge 011 = Simple Capture mode: capture on every rising edge 010 = Simple Capture mode: capture on every falling edge 001 = Edge Detect Capture mode: capture on every edge (rising and falling), ICI1:ICI0 bits do not control interrupt generation for this mode 000 = Input capture module turned off The ICx input must also be configured to an available RPn pin. For more information, see Section 9.4 "Peripheral Pin Select".
bit 12-10
bit 9-7 bit 6-5
bit 4
bit 3
bit 2-0
Note 1:
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REGISTER 12-2:
U-0 -- bit 15 R/W-0 ICTRIG bit 7 Legend: R = Readable bit -n = Value at POR bit 15-9 bit 8 W = Writable bit `1' = Bit is set HS = Hardware Settable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 HS TRIGSTAT U-0 -- R/W-0 SYNCSEL4 R/W-0 SYNCSEL3 R/W-0 SYNCSEL2 R/W-0 SYNCSEL1
ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 IC32 bit 8 R/W-0 SYNCSEL0 bit 0
Unimplemented: Read as `0' IC32: Cascade Two IC Modules Enable bit (32-bit operation) 1 = ICx and ICy operate in cascade as a 32-bit module (this bit must be set in both modules) 0 = ICx functions independently as a 16-bit module ICTRIG: ICx Trigger/Sync Select bit 1 = Trigger ICx from source designated by SYNCSELx bits 0 = Synchronize ICx with source designated by SYNCSELx bits TRIGSTAT: Timer Trigger Status bit 1 = Timer source has been triggered and is running (set in hardware, can be set in software) 0 = Timer source has not been triggered and is being held clear Unimplemented: Read as `0' SYNCSEL4:SYNCSEL0: Trigger/Synchronization Source Selection bits 11111 = Reserved 11110 = Input Capture 9 11101 = Input Capture 6 11100 = CTMU(1) 11011 = A/D(1) 11010 = Comparator 3(1) 11001 = Comparator 2(1) 11000 = Comparator 1(1) 10111 = Input Capture 4 10110 = Input Capture 3 10101 = Input Capture 2 10100 = Input Capture 1 10011 = Input Capture 8 10010 = Input Capture 7 1000x = reserved 01111 = Timer 5 01110 = Timer 4 01101 = Timer 3 01100 = Timer 2 01011 = Timer 1 01010 = Input Capture 5 01001 = Output Compare 9 01000 = Output Compare 8 00111 = Output Compare 7 00110 = Output Compare 6 00101 = Output Compare 5 00100 = Output Compare 4 00011 = Output Compare 3 00010 = Output Compare 2 00001 = Output Compare 1 00000 = Not synchronized to any other module Use these inputs as trigger sources only and never as sync sources.
bit 7
bit 6
bit 5 bit 4-0
Note 1:
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13.0
Note:
OUTPUT COMPARE WITH DEDICATED TIMERS
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual".
In Synchronous mode, the module begins performing its compare or PWM operation as soon as its selected clock source is enabled. Whenever an event occurs on the selected sync source, the module's internal counter is reset. In Trigger mode, the module waits for a sync event from another internal module to occur before allowing the counter to run. Free-running mode is selected by default, or any time that the SYNCSEL bits (OCxCON2<4:0>) are set to `00000'. Synchronous or Trigger modes are selected any time the SYNCSEL bits are set to any value except `00000'. The OCTRIG bit (OCxCON2<7>) selects either Synchronous or Trigger mode; setting the bit selects Trigger mode operation. In both modes, the SYNCSEL bits determine the sync/trigger source.
Devices in the PIC24FJ256GB110 family all feature 9 independent output compare modules. Each of these modules offers a wide range of configuration and operating options for generating pulse trains on internal device events, and can produce pulse-width modulated waveforms for driving power applications. Key features of the output compare module include: * Hardware-configurable for 32-bit operation in all modes by cascading two adjacent modules * Synchronous and Trigger modes of output compare operation, with up to 30 user-selectable trigger/sync sources available * Two separate period registers (a main register, OCxR, and a secondary register, OCxRS) for greater flexibility in generating pulses of varying widths * Configurable for single-pulse or continuous pulse generation on an output event, or continuous PWM waveform generation * Up to 6 clock sources available for each module, driving a separate internal 16-bit counter
13.1.2
CASCADED (32-BIT) MODE
By default, each module operates independently with its own set of 16-bit timer and duty cycle registers. To increase resolution, adjacent even and odd modules can be configured to function as a single 32-bit module. (For example, modules 1 and 2 are paired, as are modules 3 and 4, and so on.) The odd-numbered module (OCx) provides the Least Significant 16 bits of the 32-bit register pairs, and the even module (OCy) provides the Most Significant 16 bits. Wraparounds of the OCx registers cause an increment of their corresponding OCy registers. Cascaded operation is configured in hardware by setting the OC32 bits (OCxCON2<8>) for both modules.
13.1
13.1.1
General Operating Modes
SYNCHRONOUS AND TRIGGER MODES
By default, the output compare module operates in a free-running mode. The internal 16-bit counter, OCxTMR, runs counts up continuously, wrapping around from FFFFh to 0000h on each overflow, with its period synchronized to the selected external clock source. Compare or PWM events are generated each time a match between the internal counter and one of the period registers occurs.
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FIGURE 13-1: OUTPUT COMPARE BLOCK DIAGRAM (16-BIT MODE)
OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLT0 OCFLT0 Match Event
OCxCON1
OCTSELx SYNCSELx TRIGSTAT TRIGMODE OCTRIG
OCxCON2
OCxR Comparator
OCx Pin(1)
OC Clock Sources
Clock Select
Increment
OCxTMR
Reset
OC Output and Fault Logic
Match Event
Match Event
Comparator OCxRS
OCFA/OCFB
Trigger and Sync Sources
Trigger and Sync Logic
Reset
OCx Interrupt
Note 1:
The OCx outputs must be assigned to an available RPn pin before use. Please see Section 9.4 "Peripheral Pin Select" for more information.
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13.2 Compare Operations
In Compare mode (Figure 13-1), the output compare module can be configured for single-shot or continuous pulse generation; it can also repeatedly toggle an output pin on each timer event. To set up the module for compare operations: 1. 2. Configure the OCx output for one of the available Peripheral Pin Select pins. Calculate the required values for the OCxR and (for Double Compare modes) OCxRS duty cycle registers: a) Determine the instruction clock cycle time. Take into account the frequency of the external clock to the timer source (if one is used) and the timer prescaler settings. b) Calculate time to the rising edge of the output pulse relative to the timer start value (0000h). c) Calculate the time to the falling edge of the pulse based on the desired pulse width and the time to the rising edge of the pulse. Write the rising edge value to OCxR, and the falling edge value to OCxRS. Set the Timer Period register, PRy, to a value equal to or greater than the value in OCxRS. Set the OCM2:OCM0 bits for the appropriate compare operation (= 0xx). For Trigger mode operations, set OCTRIG to enable Trigger mode. Set or clear TRIGMODE to configure trigger operation, and TRIGSTAT to select a hardware or software trigger. For Synchronous mode, clear OCTRIG. Set the SYNCSEL4:SYNCSEL0 bits to configure the trigger or synchronization source. If free-running timer operation is required, set the SYNCSEL bits to `00000' (no sync/trigger source). Select the time base source with the OCTSEL2:OCTSEL0 bits. If necessary, set the TON bit for the selected timer which enables the compare time base to count. Synchronous mode operation starts as soon as the time base is enabled; Trigger mode operation starts after a trigger source event occurs. For 32-bit cascaded operation, these steps are also necessary: 1. Set the OC32 bits for both registers (OCyCON2<8> and (OCxCON2<8>). Enable the even-numbered module first to ensure the modules will start functioning in unison. Clear the OCTRIG bit of the even module (OCyCON2), so the module will run in Synchronous mode. Configure the desired output and Fault settings for OCy. Force the output pin for OCx to the output state by clearing the OCTRIS bit. If Trigger mode operation is required, configure the trigger options in OCx by using the OCTRIG (OCxCON2<7>), TRIGSTAT (OCxCON2<6>), and SYNCSEL (OCxCON2<4:0>) bits. Configure the desired compare or PWM mode of operation (OCM<2:0>) for OCy first, then for OCx.
2.
3. 4. 5.
6.
3. 4. 5. 6.
Depending on the output mode selected, the module holds the OCx pin in its default state, and forces a transition to the opposite state when OCxR matches the timer. In Double Compare modes, OCx is forced back to its default state when a match with OCxRS occurs. The OCxIF interrupt flag is set after an OCxR match in Single Compare modes, and after each OCxRS match in Double Compare modes. Single-shot pulse events only occur once, but may be repeated by simply rewriting the value of the OCxCON1 register. Continuous pulse events continue indefinitely until terminated.
7.
8.
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13.3 Pulse-Width Modulation (PWM) Mode
5. 6. Select a clock source by writing the OCTSEL2<2:0> (OCxCON<12:10>) bits. Enable interrupts, if required, for the timer and output compare modules. The output compare interrupt is required for PWM Fault pin utilization. Select the desired PWM mode in the OCM<2:0> (OCxCON1<2:0>) bits. If a timer is selected as a clock source, set the TMRy prescale value and enable the time base by setting the TON (TxCON<15>) bit. Note: This peripheral contains input and output functions that may need to be configured by the peripheral pin select. See Section 9.4 "Peripheral Pin Select" for more information.
In PWM mode, the output compare module can be configured for edge-aligned or center-aligned pulse waveform generation. All PWM operations are double-buffered (buffer registers are internal to the module and are not mapped into SFR space). To configure the output compare module for PWM operation: 1. 2. 3. 4. Configure the OCx output for one of the available Peripheral Pin Select pins. Calculate the desired duty cycles and load them into the OCxR register. Calculate the desired period and load it into the OCxRS register. Select the current OCx as the trigger/sync source by writing 0x1F to SYNCSEL<4:0> (OCxCON2<4:0>).
7. 8.
FIGURE 13-2:
OUTPUT COMPARE BLOCK DIAGRAM (DOUBLE-BUFFERED, 16-BIT PWM MODE)
OCxCON1 OCxCON2
OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLT0 OCFLT0
OCTSELx SYNCSELx TRIGSTAT TRIGMODE OCTRIG
OCxR
Rollover/Reset
OCxR buffer Comparator
OCx Pin OC Clock Sources Clock Select
Increment Match Event Rollover
OCxTMR
Reset Match Event
OC Output and Fault Logic OCFA/OCFB
Comparator OCxRS buffer
Trigger and Sync Sources
Trigger and Sync Logic
Match Event
Rollover/Reset
OCxRS OCx Interrupt
Reset
Note 1:
The OCx outputs must be assigned to an available RPn pin before use. Please see Section 9.4 "Peripheral Pin Select" for more information.
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13.3.1 PWM PERIOD 13.3.2 PWM DUTY CYCLE
The PWM period is specified by writing to PRy, the Timer Period register. The PWM period can be calculated using Equation 13-1. The PWM duty cycle is specified by writing to the OCxRS and OCxR registers. The OCxRS and OCxR registers can be written to at any time, but the duty cycle value is not latched until a match between PRy and TMRy occurs (i.e., the period is complete). This provides a double buffer for the PWM duty cycle and is essential for glitchless PWM operation. Some important boundary parameters of the PWM duty cycle include: * If OCxR, OCxRS, and PRy are all loaded with 0000h, the OCx pin will remain low (0% duty cycle). * *If OCxRS is greater than PRy, the pin will remain high (100% duty cycle). See Example 13-1 for PWM mode timing details. Table 13-1 and Table 13-2 show example PWM frequencies and resolutions for a device operating at 4 MIPS and 10 MIPS, respectively.
EQUATION 13-1:
CALCULATING THE PWM PERIOD(1)
PWM Period = [(PRy) + 1] * TCY * (Timer Prescale Value) where: PWM Frequency = 1/[PWM Period] Note 1: Based on TCY = TOSC * 2, Doze mode and PLL are disabled. A PRy value of N will produce a PWM period of N + 1 time base count cycles. For example, a value of 7 written into the PRy register will yield a period consisting of 8 time base cycles.
Note:
EQUATION 13-2:
CALCULATION FOR MAXIMUM PWM RESOLUTION(1)
log10 Maximum PWM Resolution (bits) = FCY (FPWM * (Timer Prescale Value)) bits log10(2)
Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.
EXAMPLE 13-1:
PWM PERIOD AND DUTY CYCLE CALCULATIONS(1)
1. Find the Timer Period register value for a desired PWM frequency of 52.08 kHz, where FOSC = 8 MHz with PLL (32 MHz device clock rate) and a Timer2 prescaler setting of 1:1. TCY = 2 * TOSC = 62.5 ns PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 s PWM Period = (PR2 + 1) * TCY * (Timer 2 Prescale Value) 19.2 s = (PR2 + 1) * 62.5 ns * 1 PR2 = 306 2. Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz device clock rate: PWM Resolution = log10 (FCY/FPWM)/log102) bits = (log10 (16 MHz/52.08 kHz)/log102) bits = 8.3 bits Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled.
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TABLE 13-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)(1)
7.6 Hz 8 FFFFh 16 61 Hz 1 FFFFh 16 122 Hz 1 7FFFh 15 977 Hz 1 0FFFh 12 3.9 kHz 1 03FFh 10 31.3 kHz 1 007Fh 7 125 kHz 1 001Fh 5 PWM Frequency Timer Prescaler Ratio Period Register Value Resolution (bits) Note 1:
Based on FCY = FOSC/2, Doze mode and PLL are disabled.
TABLE 13-2:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz)(1)
30.5 Hz 8 FFFFh 16 244 Hz 1 FFFFh 16 488 Hz 1 7FFFh 15 3.9 kHz 1 0FFFh 12 15.6 kHz 1 03FFh 10 125 kHz 1 007Fh 7 500 kHz 1 001Fh 5
PWM Frequency Timer Prescaler Ratio Period Register Value Resolution (bits) Note 1:
Based on FCY = FOSC/2, Doze mode and PLL are disabled.
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REGISTER 13-1:
U-0 -- bit 15 R/W-0 ENFLT0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13
OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1
U-0 -- R/W-0 OCSIDL R/W-0 OCTSEL2 R/W-0 OCTSEL1 R/W-0 OCTSEL0 U-0 -- U-0 -- bit 8 U-0 -- U-0 -- R/W-0, HCS OCFLT0 R/W-0 TRIGMODE R/W-0 OCM2(1) R/W-0 OCM1(1) R/W-0 OCM0(1) bit 0
W = Writable bit `1' = Bit is set
HCS = Hardware Clearable/Settable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 12-10
bit 9-8 bit 7
bit 6-5 bit 4
bit 3
bit 2-0
Unimplemented: Read as `0' OCSIDL: Stop Output Compare x in Idle Mode Control bit 1 = Output Compare x halts in CPU Idle mode 0 = Output Compare x continues to operate in CPU Idle mode OCTSEL2:OCTSEL0: Output Compare x Timer Select bits 111 = System Clock 110 = Reserved 101 = Reserved 100 = Timer1 011 = Timer5 010 = Timer4 001 = Timer3 000 = Timer2 Unimplemented: Read as `0' ENFLT0: Fault 0 Input Enable bit 1 = Fault 0 input is enabled 0 = Fault 0 input is disabled Unimplemented: Read as `0' OCFLT0: PWM Fault Condition Status bit 1 = PWM Fault condition has occurred (cleared in HW only) 0 = No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111) TRIGMODE: Trigger Status Mode Select bit 1 = TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software 0 = TRIGSTAT is only cleared by software OCM2:OCM0: Output Compare x Mode Select bits(1) 111 = Center-aligned PWM mode on OCx(2) 110 = Edge-aligned PWM Mode on OCx(2) 101 = Double Compare Continuous Pulse mode: Initialize OCx pin low, toggle OCx state continuously on alternate matches of OCxR and OCxRS 100 = Double Compare Single-Shot mode: Initialize OCx pin low, toggle OCx state on matches of OCxR and OCxRS for one cycle 011 = Single Compare Continuous Pulse mode: Compare events continuously toggle OCx pin 010 = Single Compare Single-Shot mode: Initialize OCx pin high, compare event forces OCx pin low 001 = Single Compare Single-Shot mode: Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled The OCx output must also be configured to an available RPn pin. For more information, see Section 9.4 "Peripheral Pin Select". OCFA pin controls OC1-OC4 channels; OCFB pin controls the OC5-OC9 channels. OCxR and OCxRS are double-buffered only in PWM modes.
Note 1: 2:
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REGISTER 13-2:
R/W-0 FLTMD bit 15 R/W-0 OCTRIG bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HS = Hardware Settable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 HS TRIGSTAT R/W-0 OCTRIS R/W-0 SYNCSEL4 R/W-0 SYNCSEL3 R/W-0 SYNCSEL2 R/W-0 SYNCSEL1
OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2
R/W-0 FLTTRIEN R/W-0 OCINV U-0
--
R/W-0 FLTOUT
U-0
--
U-0
--
R/W-0 OC32 bit 8 R/W-0 SYNCSEL0 bit 0
FLTMD: Fault Mode Select bit 1 = Fault mode is maintained until the Fault source is removed and the corresponding OCFLT0 bit is cleared in software 0 = Fault mode is maintained until the Fault source is removed and a new PWM period starts FLTOUT: Fault Out bit 1 = PWM output is driven high on a Fault 0 = PWM output is driven low on a Fault FLTTRIEN: Fault Output State Select bit 1 = Pin is forced to an output on a Fault condition 0 = Pin I/O condition is unaffected by a Fault OCINV: OCMP Invert bit 1 = OCx output is inverted 0 = OCx output is not inverted Unimplemented: Read as `0' OC32: Cascade Two OC Modules Enable bit (32-bit operation) 1 = Cascade module operation enabled 0 = Cascade module operation disabled OCTRIG: OCx Trigger/Sync Select bit 1 = Trigger OCx from source designated by SYNCSELx bits 0 = Synchronize OCx with source designated by SYNCSELx bits TRIGSTAT: Timer Trigger Status bit 1 = Timer source has been triggered and is running 0 = Timer source has not been triggered and is being held clear OCTRIS: OCx Output Pin Direction Select bit 1 = OCx pin is tristated 0 = Output compare peripheral x connected to OCx pin
bit 14
bit 13
bit 12
bit 11-9 bit 8
bit 7
bit 6
bit 5
Note 1: 2:
Never use an OC module as its own trigger source, either by selecting this mode or another equivalent SYNCSEL setting. Use these inputs as trigger sources only and never as sync sources.
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REGISTER 13-2:
bit 4-0
OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2
SYNCSEL4:SYNCSEL0: Trigger/Synchronization Source Selection bits 11111 = This OC module(1) 11110 = Input Capture 9(2) 11101 = Input Capture 6(2) 11100 = CTMU(2) 11011 = A/D(2) 11010 = Comparator 3(2) 11001 = Comparator 2(2) 11000 = Comparator 1(2) 10111 = Input Capture 4(2) 10110 = Input Capture 3(2) 10101 = Input Capture 2(2) 10100 = Input Capture 1(2) 10011 = Input Capture 8(2) 10010 = Input Capture 7(2) 1000x = reserved 01111 = Timer 5 01110 = Timer 4 01101 = Timer 3 01100 = Timer 2 01011 = Timer 1 01010 = Input Capture 5(2) 01001 = Output Compare 9(1) 01000 = Output Compare 8(1) 00111 = Output Compare 7(1) 00110 = Output Compare 6(1) 00101 = Output Compare 5(1) 00100 = Output Compare 4(1) 00011 = Output Compare 3(1) 00010 = Output Compare 2(1) 00001 = Output Compare 1(1) 00000 = Not synchronized to any other module Never use an OC module as its own trigger source, either by selecting this mode or another equivalent SYNCSEL setting. Use these inputs as trigger sources only and never as sync sources.
Note 1: 2:
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NOTES:
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14.0
Note:
SERIAL PERIPHERAL INTERFACE (SPI)
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 23. Serial Peripheral Interface (SPI)" (DS39699).
The SPI serial interface consists of four pins: * * * * SDIx: Serial Data Input SDOx: Serial Data Output SCKx: Shift Clock Input or Output SSx: Active-Low Slave Select or Frame Synchronization I/O Pulse
The SPI module can be configured to operate using 2, 3 or 4 pins. In the 3-pin mode, SSx is not used. In the 2-pin mode, both SDOx and SSx are not used. Block diagrams of the module in Standard and Enhanced modes are shown in Figure 14-1 and Figure 14-2. Note: In this section, the SPI modules are referred to together as SPIx or separately as SPI1, SPI2 or SPI3. Special Function Registers will follow a similar notation. For example, SPIxCON1 and SPIxCON2 refer to the control registers for any of the 3 SPI modules.
The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D Converters, etc. The SPI module is compatible with Motorola's SPI and SIOP interfaces. All devices of the PIC24FJ256GB110 family include three SPI modules The module supports operation in two buffer modes. In Standard mode, data is shifted through a single serial buffer. In Enhanced Buffer mode, data is shifted through an 8-level FIFO buffer. Note: Do not perform read-modify-write operations (such as bit-oriented instructions) on the SPIxBUF register in either Standard or Enhanced Buffer mode.
The module also supports a basic framed SPI protocol while operating in either Master or Slave mode. A total of four framed SPI configurations are supported.
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To set up the SPI module for the Standard Master mode of operation: 1. If using interrupts: a) Clear the SPIxIF bit in the respective IFS register. b) Set the SPIxIE bit in the respective IEC register. c) Write the SPIxIP bits in the respective IPC register to set the interrupt priority. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1<5>) = 1. Clear the SPIROV bit (SPIxSTAT<6>). Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>). Write the data to be transmitted to the SPIxBUF register. Transmission (and reception) will start as soon as data is written to the SPIxBUF register. To set up the SPI module for the Standard Slave mode of operation: 1. 2. Clear the SPIxBUF register. If using interrupts: a) Clear the SPIxIF bit in the respective IFS register. b) Set the SPIxIE bit in the respective IEC register. c) Write the SPIxIP bits in the respective IPC register to set the interrupt priority. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1<5>) = 0. Clear the SMP bit. If the CKE bit (SPIxCON1<8>) is set, then the SSEN bit (SPIxCON1<7>) must be set to enable the SSx pin. Clear the SPIROV bit (SPIxSTAT<6>). Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>).
2.
3.
3. 4. 5.
4. 5.
6. 7.
FIGURE 14-1:
SCKx
SPIx MODULE BLOCK DIAGRAM (STANDARD MODE)
1:1 to 1:8 Secondary Prescaler Sync Control Control Clock Shift Control Select Edge 1:1/4/16/64 Primary Prescaler
FCY
SSx/FSYNCx
SPIxCON1<1:0> SPIxCON1<4:2> Enable Master Clock
SDOx SDIx bit 0
SPIxSR
Transfer
Transfer
SPIxBUF
Read SPIxBUF
Write SPIxBUF 16 Internal Data Bus
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To set up the SPI module for the Enhanced Buffer Master mode of operation: 1. If using interrupts: a) Clear the SPIxIF bit in the respective IFS register. b) Set the SPIxIE bit in the respective IEC register. c) Write the SPIxIP bits in the respective IPC register. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1<5>) = 1. Clear the SPIROV bit (SPIxSTAT<6>). Select Enhanced Buffer mode by setting the SPIBEN bit (SPIxCON2<0>). Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>). Write the data to be transmitted to the SPIxBUF register. Transmission (and reception) will start as soon as data is written to the SPIxBUF register. To set up the SPI module for the Enhanced Buffer Slave mode of operation: 1. 2. Clear the SPIxBUF register. If using interrupts: a) Clear the SPIxIF bit in the respective IFS register. b) Set the SPIxIE bit in the respective IEC register. c) Write the SPIxIP bits in the respective IPC register to set the interrupt priority. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1<5>) = 0. Clear the SMP bit. If the CKE bit is set, then the SSEN bit must be set, thus enabling the SSx pin. Clear the SPIROV bit (SPIxSTAT<6>). Select Enhanced Buffer mode by setting the SPIBEN bit (SPIxCON2<0>). Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>).
2.
3.
3. 4. 5. 6.
4. 5. 6. 7. 8.
FIGURE 14-2:
SCKx
SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)
1:1 to 1:8 Secondary Prescaler Sync Control Control Clock Shift Control Select Edge 1:1/4/16/64 Primary Prescaler FCY
SSx/FSYNCx
SPIxCON1<1:0> SPIxCON1<4:2> Enable Master Clock
SDOx SDIx bit0
SPIxSR
Transfer
Transfer
8-Level FIFO Receive Buffer
8-Level FIFO Transmit Buffer
SPIxBUF
Read SPIxBUF
Write SPIxBUF 16 Internal Data Bus
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REGISTER 14-1:
R/W-0 SPIEN bit 15 R-0 SRMPT bit 7 Legend: R = Readable bit -n = Value at POR bit 15 C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/C-0 SPIROV R/W-0 SRXMPT R/W-0 SISEL2 R/W-0 SISEL1 R/W-0 SISEL0 R-0 SPITBF R-0 SPIRBF bit 0
(1)
SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
U-0 -- R/W-0 SPISIDL U-0 -- U-0 -- R-0 SPIBEC2 R-0 SPIBEC1 R-0 SPIBEC0 bit 8
SPIEN: SPIx Enable bit(1) 1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables module Unimplemented: Read as `0' SPISIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' SPIBEC2:SPIBEC0: SPIx Buffer Element Count bits (valid in Enhanced Buffer mode) Master mode: Number of SPI transfers pending. Slave mode: Number of SPI transfers unread. SRMPT: Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode) 1 = SPIx Shift register is empty and ready to send or receive 0 = SPIx Shift register is not empty SPIROV: Receive Overflow Flag bit 1 = A new byte/word is completely received and discarded. The user software has not read the previous data in the SPIxBUF register. 0 = No overflow has occurred SRXMPT: Receive FIFO Empty bit (valid in Enhanced Buffer mode) 1 = Receive FIFO is empty 0 = Receive FIFO is not empty SISEL2:SISEL0: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode) 111 = Interrupt when SPIx transmit buffer is full (SPITBF bit is set) 110 = Interrupt when last bit is shifted into SPIxSR, as a result, the TX FIFO is empty 101 = Interrupt when the last bit is shifted out of SPIxSR, now the transmit is complete 100 = Interrupt when one data is shifted into the SPIxSR, as a result, the TX FIFO has one open spot 011 = Interrupt when SPIx receive buffer is full (SPIRBF bit set) 010 = Interrupt when SPIx receive buffer is 3/4 or more full 001 = Interrupt when data is available in receive buffer (SRMPT bit is set) 000 = Interrupt when the last data in the receive buffer is read, as a result, the buffer is empty (SRXMPT bit set) If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 9.4 "Peripheral Pin Select" for more information.
bit 14 bit 13
bit 12-11 bit 10-8
bit 7
bit 6
bit 5
bit 4-2
Note 1:
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REGISTER 14-1:
bit 1
SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED)
SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit not yet started, SPIxTXB is full 0 = Transmit started, SPIxTXB is empty In Standard Buffer mode: Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR. In Enhanced Buffer mode: Automatically set in hardware when CPU writes SPIxBUF location, loading the last available buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write. SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty In Standard Buffer mode: Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB. In Enhanced Buffer mode: Automatically set in hardware when SPIx transfers data from SPIxSR to buffer, filling the last unread buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR. If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 9.4 "Peripheral Pin Select" for more information.
bit 0
Note 1:
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REGISTER 14-2:
U-0 -- bit 15 R/W-0 SSEN bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
(4)
SPIXCON1: SPIx CONTROL REGISTER 1
U-0 -- U-0 -- R/W-0 DISSCK(1) R/W-0 DISSDO(2) R/W-0 MODE16 R/W-0 SMP R/W-0 CKE(3) bit 8
R/W-0 CKP
R/W-0 MSTEN
R/W-0 SPRE2
R/W-0 SPRE1
R/W-0 SPRE0
R/W-0 PPRE1
R/W-0 PPRE0 bit 0
Unimplemented: Read as `0' DISSCK: Disable SCKx pin bit (SPI Master modes only)(1) 1 = Internal SPI clock is disabled; pin functions as I/O 0 = Internal SPI clock is enabled DISSDO: Disable SDOx pin bit(2) 1 = SDOx pin is not used by module; pin functions as I/O 0 = SDOx pin is controlled by the module MODE16: Word/Byte Communication Select bit 1 = Communication is word-wide (16 bits) 0 = Communication is byte-wide (8 bits) SMP: SPIx Data Input Sample Phase bit Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time Slave mode: SMP must be cleared when SPIx is used in Slave mode. CKE: SPIx Clock Edge Select bit(3) 1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6) 0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6) SSEN: Slave Select Enable (Slave mode) bit(4) 1 = SSx pin used for Slave mode 0 = SSx pin not used by module; pin controlled by port function CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 9.4 "Peripheral Pin Select" for more information. If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section 9.4 "Peripheral Pin Select" for more information. The CKE bit is not used in the Framed SPI modes. The user should program this bit to `0' for the Framed SPI modes (FRMEN = 1). If SSEN = 1, SSx must be configured to an available RPn pin. See Section 9.4 "Peripheral Pin Select" for more information.
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
Note 1: 2: 3: 4:
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REGISTER 14-2:
bit 4-2
SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED)
SPRE2:SPRE0: Secondary Prescale bits (Master mode) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 ... 000 = Secondary prescale 8:1 PPRE1:PPRE0: Primary Prescale bits (Master mode) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 9.4 "Peripheral Pin Select" for more information. If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section 9.4 "Peripheral Pin Select" for more information. The CKE bit is not used in the Framed SPI modes. The user should program this bit to `0' for the Framed SPI modes (FRMEN = 1). If SSEN = 1, SSx must be configured to an available RPn pin. See Section 9.4 "Peripheral Pin Select" for more information.
bit 1-0
Note 1: 2: 3: 4:
REGISTER 14-3:
R/W-0 FRMEN bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15
SPIxCON2: SPIx CONTROL REGISTER 2
R/W-0 SPIFPOL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 SPIFE R/W-0 SPIBEN bit 0
R/W-0 SPIFSD
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
FRMEN: Framed SPIx Support bit 1 = Framed SPIx support enabled 0 = Framed SPIx support disabled SPIFSD: Frame Sync Pulse Direction Control on SSx pin bit 1 = Frame sync pulse input (slave) 0 = Frame sync pulse output (master) SPIFPOL: Frame Sync Pulse Polarity bit (Frame mode only) 1 = Frame sync pulse is active-high 0 = Frame sync pulse is active-low Unimplemented: Read as `0' SPIFE: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced Buffer enabled 0 = Enhanced Buffer disabled (Legacy mode)
bit 14
bit 13
bit 12-2 bit 1
bit 0
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FIGURE 14-3: SPI MASTER/SLAVE CONNECTION (STANDARD MODE)
PROCESSOR 1 (SPI Master) PROCESSOR 2 (SPI Slave)
SDOx
SDIx
Serial Receive Buffer (SPIxRXB)
Serial Receive Buffer (SPIxRXB)
Shift Register (SPIxSR) MSb LSb
SDIx
SDOx MSb
Shift Register (SPIxSR) LSb
Serial Transmit Buffer (SPIxTXB)
Serial Transmit Buffer (SPIxTXB)
SPIx Buffer (SPIxBUF)
SCKx
Serial Clock
SCKx
SPIx Buffer (SPIxBUF)
SSx MSTEN (SPIxCON1<5>) = 1) Note 1: 2: SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0
Using the SSx pin in Slave mode of operation is optional. User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF.
FIGURE 14-4:
SPI MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES)
PROCESSOR 2 (SPI Enhanced Buffer Slave)
SDIx
PROCESSOR 1 (SPI Enhanced Buffer Master)
SDOx
Shift Register (SPIxSR) MSb LSb
SDIx
SDOx
Shift Register (SPIxSR) MSb LSb
8-Level FIFO Buffer
8-Level FIFO Buffer
SPIx Buffer (SPIxBUF)
SCKx
Serial Clock
SCKx
SPIx Buffer (SPIxBUF)
SSx
SSx
MSTEN (SPIxCON1<5>) = 1 and SPIBEN (SPIxCON2<0>) = 1 Note 1: 2:
SSEN (SPIxCON1<7>) = 1, MSTEN (SPIxCON1<5>) = 0 and SPIBEN (SPIxCON2<0>) = 1
Using the SSx pin in Slave mode of operation is optional. User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF.
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FIGURE 14-5: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM
PIC24F (SPI Slave, Frame Slave) SDOx SDIx PROCESSOR 2
SDIx SCKx SSx Serial Clock
SDOx SCKx SSx
Frame Sync Pulse
FIGURE 14-6:
SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM
PIC24F SPI Master, Frame Slave) SDOx SDIx SCKx SSx Serial Clock SDIx SDOx SCKx SSx PROCESSOR 2
Frame Sync Pulse
FIGURE 14-7:
SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM
PIC24F (SPI Slave, Frame Slave) SDOx SDIx PROCESSOR 2
SDIx SCKx SSx Serial Clock
SDOx SCKx SSx
Frame Sync. Pulse
FIGURE 14-8:
SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM
PIC24F (SPI Master, Frame Slave) SDOx SDIx PROCESSOR 2
SDIx SCKx SSx Serial Clock
SDOx SCKx SSx
Frame Sync Pulse
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EQUATION 14-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED(1)
FSCK = FCY Primary Prescaler * Secondary Prescaler
Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.
TABLE 14-1:
SAMPLE SCK FREQUENCIES(1,2)
FCY = 16 MHz Secondary Prescaler Settings 1:1 1:1 4:1 16:1 64:1 FCY = 5 MHz Invalid 4000 1000 250 2:1 8000 2000 500 125 4:1 4000 1000 250 63 6:1 2667 667 167 42 8:1 2000 500 125 31
Primary Prescaler Settings
Primary Prescaler Settings
1:1 4:1 16:1 64:1
5000 1250 313 78
2500 625 156 39
1250 313 78 20
833 208 52 13
625 156 39 10
Note 1: 2:
Based on FCY = FOSC/2, Doze mode and PLL are disabled. SCKx frequencies shown in kHz.
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15.0
Note:
INTER-INTEGRATED CIRCUIT (I2CTM)
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 24. Inter-Integrated Circuit (I2CTM)" (DS39702).
15.1
Communicating as a Master in a Single Master Environment
The details of sending a message in Master mode depends on the communications protocol for the device being communicated with. Typically, the sequence of events is as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Assert a Start condition on SDAx and SCLx. Send the I 2C device address byte to the slave with a write indication. Wait for and verify an Acknowledge from the slave. Send the first data byte (sometimes known as the command) to the slave. Wait for and verify an Acknowledge from the slave. Send the serial memory address low byte to the slave. Repeat steps 4 and 5 until all data bytes are sent. Assert a Repeated Start condition on SDAx and SCLx. Send the device address byte to the slave with a read indication. Wait for and verify an Acknowledge from the slave. Enable master reception to receive serial memory data. Generate an ACK or NACK condition at the end of a received byte of data. Generate a Stop condition on SDAx and SCLx.
The Inter-Integrated Circuit (I2C) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, display drivers, A/D Converters, etc. The I * * * * * * * * *
2C
module supports these features:
Independent master and slave logic 7-bit and 10-bit device addresses General call address, as defined in the I2C protocol Clock stretching to provide delays for the processor to respond to a slave data request Both 100 kHz and 400 kHz bus specifications. Configurable address masking Multi-Master modes to prevent loss of messages in arbitration Bus Repeater mode, allowing the acceptance of all messages as a slave regardless of the address Automatic SCL
A block diagram of the module is shown in Figure 15-1.
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FIGURE 15-1: I2CTM BLOCK DIAGRAM
Internal Data Bus I2CxRCV Shift Clock I2CxRSR LSB SDAx Address Match
Read
SCLx
Match Detect
Write I2CxMSK Write Read
I2CxADD Read Start and Stop Bit Detect Start and Stop Bit Generation Control Logic
Write I2CxSTAT Read Write I2CxCON Read
Collision Detect
Acknowledge Generation Clock Stretching
Write
I2CxTRN LSB Shift Clock Reload Control Read
Write I2CxBRG Read
BRG Down Counter
TCY/2
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15.2 Setting Baud Rate When Operating as a Bus Master 15.3 Slave Address Masking
The I2CxMSK register (Register 15-3) designates address bit positions as "don't care" for both 7-Bit and 10-Bit Addressing modes. Setting a particular bit location (= 1) in the I2CxMSK register causes the slave module to respond whether the corresponding address bit value is a `0' or a `1'. For example, when I2CxMSK is set to `00100000', the slave module will detect both addresses, `0000000' and `0100000'. To enable address masking, the IPMI (Intelligent Peripheral Management Interface) must be disabled by clearing the IPMIEN bit (I2CxCON<11>). Note: As a result of changes in the I2CTM protocol, the addresses in Table 15-2 are reserved and will not be acknowledged in Slave mode. This includes any address mask settings that include any of these addresses.
To compute the Baud Rate Generator reload value, use Equation 15-1.
EQUATION 15-1:
COMPUTING BAUD RATE RELOAD VALUE(1,2)
FCY FSCL = --------------------------------------------------------------------FCY I2CxBRG + 1 + ----------------------------10, 000, 000 or FCY FCY I2CxBRG = ----------- - ----------------------------- - 1 FSCL 10, 000, 000 Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. 2: These clock rate values are for guidance only. The actual clock rate can be affected by various system level parameters. The actual clock rate should be measured in its intended application.
TABLE 15-1:
I2CTM CLOCK RATES(1,2)
FCY 16 MHz 8 MHz 4 MHz 16 MHz 8 MHz 4 MHz 2 MHz 16 MHz 8 MHz I2CxBRG Value (Decimal) 157 78 39 37 18 9 4 13 6 (Hexadecimal) 9D 4E 27 25 12 9 4 D 6 Actual FSCL 100 kHz 100 kHz 99 kHz 404 kHz 404 kHz 385 kHz 385 kHz 1.026 MHz 1.026 MHz
Required System FSCL 100 kHz 100 kHz 100 kHz 400 kHz 400 kHz 400 kHz 400 kHz 1 MHz 1 MHz
1 MHz 4 MHz 3 3 0.909 MHz Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled. 2: These clock rate values are for guidance only. The actual clock rate can be affected by various system level parameters. The actual clock rate should be measured in its intended application.
TABLE 15-2:
Slave Address 0000 000 0000 000 0000 001 0000 010 0000 011 0000 1xx 1111 1xx 1111 Note 1: 2: 3:
I2CTM RESERVED ADDRESSES(1)
R/W Bit 0 1 x x x x x General Call Start Byte Cbus Address Reserved Reserved HS Mode Master Code Reserved Address(2) Description
0xx x 10-Bit Slave Upper Byte(3) The address bits listed here will never cause an address match, independent of address mask settings. Address will be Acknowledged only if GCEN = 1. Match on this address can only occur on the upper byte in 10-Bit Addressing mode.
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REGISTER 15-1:
R/W-0 I2CEN bit 15 R/W-0 GCEN bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HC = Hardware Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 STREN R/W-0 ACKDT R/W-0, HC ACKEN R/W-0, HC RCEN R/W-0, HC PEN R/W-0, HC RSEN
I2CxCON: I2Cx CONTROL REGISTER
U-0 -- R/W-0 I2CSIDL R/W-1 HC SCLREL R/W-0 IPMIEN R/W-0 A10M R/W-0 DISSLW R/W-0 SMEN bit 8 R/W-0, HC SEN bit 0
I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables I2Cx module. All I2C pins are controlled by port functions. Unimplemented: Read as `0' I2CSIDL: Stop in Idle Mode bit 1 = Discontinues module operation when device enters an Idle mode 0 = Continues module operation in Idle mode SCLREL: SCLx Release Control bit (when operating as I2C Slave) 1 = Releases SCLx clock 0 = Holds SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software may write `0' to initiate stretch and write `1' to release clock). Hardware clear at beginning of slave transmission. Hardware clear at end of slave reception. If STREN = 0: Bit is R/S (i.e., software may only write `1' to release clock). Hardware clear at beginning of slave transmission. IPMIEN: Intelligent Platform Management Interface (IPMI) Enable bit 1 = IPMI Support mode is enabled; all addresses Acknowledged 0 = IPMI mode disabled A10M: 10-Bit Slave Addressing bit 1 = I2CxADD is a 10-bit slave address 0 = I2CxADD is a 7-bit slave address DISSLW: Disable Slew Rate Control bit 1 = Slew rate control disabled 0 = Slew rate control enabled SMEN: SMBus Input Levels bit 1 = Enables I/O pin thresholds compliant with SMBus specification 0 = Disables SMBus input thresholds GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enables interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address disabled STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with SCLREL bit. 1 = Enables software or receive clock stretching 0 = Disables software or receive clock stretching
bit 14 bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
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REGISTER 15-1:
bit 5
I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
ACKDT: Acknowledge Data bit (When operating as I2C master. Applicable during master receive.) Value that will be transmitted when the software initiates an Acknowledge sequence. 1 = Sends NACK during Acknowledge 0 = Sends ACK during Acknowledge ACKEN: Acknowledge Sequence Enable bit (When operating as I2C master. Applicable during master receive.) 1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit. Hardware clear at end of master Acknowledge sequence. 0 = Acknowledge sequence not in progress RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte. 0 = Receives sequence not in progress PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiates Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence. 0 = Stop condition not in progress RSEN: Repeated Start Condition Enabled bit (when operating as I2C master) 1 = Initiates Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master Repeated Start sequence. 0 = Repeated Start condition not in progress SEN: Start Condition Enabled bit (when operating as I2C master) 1 = Initiates Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence. 0 = Start condition not in progress
bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 15-2:
R-0, HSC ACKSTAT bit 15 R/C-0, HS IWCOL bit 7 Legend: R = Readable bit -n = Value at POR bit 15 C = Clearable bit W = Writable bit `1' = Bit is set HS = Hardware Settable bit HSC = Hardware Settable/ Clearable bit x = Bit is unknown R/C-0, HS I2COV R-0, HSC D/A R/C-0, HSC P R/C-0, HSC S R-0, HSC R/W R-0, HSC RBF
I2CxSTAT: I2Cx STATUS REGISTER
U-0 -- U-0 -- U-0 -- R/C-0, HS BCL R-0, HSC GCSTAT R-0, HSC ADD10 bit 8 R-0, HSC TBF bit 0
R-0, HSC TRSTAT
U = Unimplemented bit, read as `0' `0' = Bit is cleared
ACKSTAT: Acknowledge Status bit 1 = NACK was detected last 0 = ACK was detected last Hardware set or clear at end of Acknowledge. TRSTAT: Transmit Status bit (When operating as I2C master. Applicable to master transmit operation.) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge. Unimplemented: Read as `0' BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No collision Hardware set at detection of bus collision. GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware set when address matches general call address. Hardware clear at Stop detection. ADD10: 10-Bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection. IWCOL: Write Collision Detect bit 1 = An attempt to write the I2CxTRN register failed because the I2C module is busy 0 = No collision Hardware set at occurrence of write to I2CxTRN while busy (cleared by software). I2COV: Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register is still holding the previous byte 0 = No overflow Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software). D/A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was device address Hardware clear at device address match. Hardware set by write to I2CxTRN or by reception of slave byte.
bit 14
bit 13-11 bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
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REGISTER 15-2:
bit 4
I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. R/W: Read/Write Information bit (when operating as I2C slave) 1 = Read - indicates data transfer is output from slave 0 = Write - indicates data transfer is input to slave Hardware set or clear after reception of I 2C device address byte. RBF: Receive Buffer Full Status bit 1 = Receive complete, I2CxRCV is full 0 = Receive not complete, I2CxRCV is empty Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.
bit 3
bit 2
bit 1
bit 0
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REGISTER 15-3:
U-0 -- bit 15 R/W-0 AMSK7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10 bit 9-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 AMSK6 R/W-0 AMSK5 R/W-0 AMSK4 R/W-0 AMSK3 R/W-0 AMSK2 R/W-0 AMSK1
I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 AMSK9 R/W-0 AMSK8 bit 8 R/W-0 AMSK0 bit 0
Unimplemented: Read as `0' AMSK9:AMSK0: Mask for Address Bit x Select bits 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position
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16.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART)
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 21. UART" (DS39708). * Fully Integrated Baud Rate Generator with 16-Bit Prescaler * Baud Rates Ranging from 1 Mbps to 15 bps at 16 MIPS * 4-Deep, First-In-First-Out (FIFO) Transmit Data Buffer * 4-Deep FIFO Receive Data Buffer * Parity, Framing and Buffer Overrun Error Detection * Support for 9-bit mode with Address Detect (9th bit = 1) * Transmit and Receive Interrupts * Loopback mode for Diagnostic Support * Support for Sync and Break Characters * Supports Automatic Baud Rate Detection * IrDA Encoder and Decoder Logic * 16x Baud Clock Output for IrDA Support A simplified block diagram of the UART is shown in Figure 16-1. The UART module consists of these key important hardware elements: * Baud Rate Generator * Asynchronous Transmitter * Asynchronous Receiver
Note:
The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in the PIC24F device family. The UART is a full-duplex asynchronous system that can communicate with peripheral devices, such as personal computers, LIN, RS-232 and RS-485 interfaces. The module also supports a hardware flow control option with the UxCTS and UxRTS pins and also includes an IrDA(R) encoder and decoder. The primary features of the UART module are: * Full-Duplex, 8 or 9-Bit data transmission through the UxTX and UxRX pins * Even, Odd or No Parity options (for 8-bit data) * One or two Stop bits * Hardware Flow Control option with UxCTS and UxRTS pins
FIGURE 16-1:
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA(R)
Hardware Flow Control
UxRTS/BCLKx UxCTS
UARTx Receiver
UxRX
UARTx Transmitter
UxTX
Note:
The UART inputs and outputs must all be assigned to available RPn pins before use. Please see Section 9.4 "Peripheral Pin Select" for more information.
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16.1 UART Baud Rate Generator (BRG)
The UART module includes a dedicated 16-bit Baud Rate Generator. The UxBRG register controls the period of a free-running, 16-bit timer. Equation 16-1 shows the formula for computation of the baud rate with BRGH = 0. The maximum baud rate (BRGH = 0) possible is FCY/16 (for UxBRG = 0) and the minimum baud rate possible is FCY/(16 * 65536). Equation 16-2 shows the formula for computation of the baud rate with BRGH = 1.
EQUATION 16-2:
EQUATION 16-1:
Baud Rate =
UART BAUD RATE WITH BRGH = 0(1,2)
FCY 16 * (UxBRG + 1) FCY -1 16 * Baud Rate
UART BAUD RATE WITH BRGH = 1(1,2)
FCY 4 * (UxBRG + 1) FCY 4 * Baud Rate -1
Baud Rate =
UxBRG = UxBRG = Note 1: 2: Note 1: 2:
FCY denotes the instruction cycle clock frequency (FOSC/2). Based on FCY = FOSC/2, Doze mode and PLL are disabled.
FCY denotes the instruction cycle clock frequency. Based on FCY = FOSC/2, Doze mode and PLL are disabled.
Example 16-1 shows the calculation of the baud rate error for the following conditions: * FCY = 4 MHz * Desired Baud Rate = 9600
The maximum baud rate (BRGH = 1) possible is FCY/4 (for UxBRG = 0) and the minimum baud rate possible is FCY/(4 * 65536). Writing a new value to the UxBRG register causes the BRG timer to be reset (cleared). This ensures the BRG does not wait for a timer overflow before generating the new baud rate.
EXAMPLE 16-1:
Desired Baud Rate UxBRG UxBRG UxBRG
BAUD RATE ERROR CALCULATION (BRGH = 0)(1)
= FCY/(16 (UxBRG + 1)) = ((FCY/Desired Baud Rate)/16) - 1 = ((4000000/9600)/16) - 1 = 25
Solving for UxBRG value:
Calculated Baud Rate= 4000000/(16 (25 + 1)) = 9615 Error = (Calculated Baud Rate - Desired Baud Rate) Desired Baud Rate = (9615 - 9600)/9600 = 0.16% Based on FCY = FOSC/2, Doze mode and PLL are disabled.
Note 1:
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16.2
1.
Transmitting in 8-Bit Data Mode
16.5
1. 2. 3.
2. 3. 4.
5.
6.
Set up the UART: a) Write appropriate values for data, parity and Stop bits. b) Write appropriate baud rate value to the UxBRG register. c) Set up transmit and receive interrupt enable and priority bits. Enable the UART. Set the UTXEN bit (causes a transmit interrupt two cycles after being set). Write data byte to lower byte of UxTXREG word. The value will be immediately transferred to the Transmit Shift Register (TSR), and the serial bit stream will start shifting out with next rising edge of the baud clock. Alternately, the data byte may be transferred while UTXEN = 0, and then the user may set UTXEN. This will cause the serial bit stream to begin immediately because the baud clock will start from a cleared state. A transmit interrupt will be generated as per interrupt control bit, UTXISELx.
Receiving in 8-Bit or 9-Bit Data Mode
4.
5.
Set up the UART (as described in Section 16.2 "Transmitting in 8-Bit Data Mode"). Enable the UART. A receive interrupt will be generated when one or more data characters have been received as per interrupt control bit, URXISELx. Read the OERR bit to determine if an overrun error has occurred. The OERR bit must be reset in software. Read UxRXREG.
The act of reading the UxRXREG character will move the next character to the top of the receive FIFO, including a new set of PERR and FERR values.
16.6
Operation of UxCTS and UxRTS Control Pins
16.3
1. 2. 3. 4. 5.
Transmitting in 9-Bit Data Mode
6.
Set up the UART (as described in Section 16.2 "Transmitting in 8-Bit Data Mode"). Enable the UART. Set the UTXEN bit (causes a transmit interrupt). Write UxTXREG as a 16-bit value only. A word write to UxTXREG triggers the transfer of the 9-bit data to the TSR. Serial bit stream will start shifting out with the first rising edge of the baud clock. A transmit interrupt will be generated as per the setting of control bit, UTXISELx.
UARTx Clear to Send (UxCTS) and Request to Send (UxRTS) are the two hardware controlled pins that are associated with the UART module. These two pins allow the UART to operate in Simplex and Flow Control mode. They are implemented to control the transmission and reception between the Data Terminal Equipment (DTE). The UEN1:UEN0 bits in the UxMODE register configure these pins.
16.7
Infrared Support
The UART module provides two types of infrared UART support: one is the IrDA clock output to support external IrDA encoder and decoder device (legacy module support) and the other is the full implementation of the IrDA encoder and decoder. Note that because the IrDA modes require a 16x baud clock, they will only work when the BRGH bit (UxMODE<3>) is `0'.
16.7.1
16.4
Break and Sync Transmit Sequence
IRDA CLOCK OUTPUT FOR EXTERNAL IRDA SUPPORT
The following sequence will send a message frame header made up of a Break, followed by an auto-baud Sync byte. 1. 2. 3. 4. 5. Configure the UART for the desired mode. Set UTXEN and UTXBRK to set up the Break character. Load the UxTXREG with a dummy character to initiate transmission (value is ignored). Write `55h' to UxTXREG; this loads the Sync character into the transmit FIFO. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits.
To support external IrDA encoder and decoder devices, the BCLKx pin (same as the UxRTS pin) can be configured to generate the 16x baud clock. With UEN1:UEN0 = 11, the BCLKx pin will output the 16x baud clock if the UART module is enabled. It can be used to support the IrDA codec chip.
16.7.2
BUILT-IN IRDA ENCODER AND DECODER
The UART has full implementation of the IrDA encoder and decoder as part of the UART module. The built-in IrDA encoder and decoder functionality is enabled using the IREN bit (UxMODE<12>). When enabled (IREN = 1), the receive pin (UxRX) acts as the input from the infrared receiver. The transmit pin (UxTX) acts as the output to the infrared transmitter.
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REGISTER 16-1:
R/W-0 UARTEN bit 15 R/C-0, HC WAKE bit 7 Legend: R = Readable bit -n = Value at POR bit 15 C = Clearable bit W = Writable bit `1' = Bit is set HC = Hardware Clearable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 LPBACK R/W-0, HC ABAUD R/W-0 RXINV R/W-0 BRGH R/W-0 PDSEL1 R/W-0 PDSEL0
(1)
UxMODE: UARTx MODE REGISTER
U-0 -- R/W-0 USIDL R/W-0 IREN
(2)
R/W-0 RTSMD
U-0 --
R/W-0 UEN1
R/W-0 UEN0 bit 8 R/W-0 STSEL bit 0
UARTEN: UARTx Enable bit(1) 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN1:UEN0 0 = UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption minimal Unimplemented: Read as `0' USIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode IREN: IrDA(R) Encoder and Decoder Enable bit(2) 1 = IrDA encoder and decoder enabled 0 = IrDA encoder and decoder disabled RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin in Simplex mode 0 = UxRTS pin in Flow Control mode Unimplemented: Read as `0' UEN1:UEN0: UARTx Enable bits 11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin controlled by PORT latches 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by PORT latches 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins controlled by PORT latches WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit 1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge, bit cleared in hardware on following rising edge 0 = No wake-up enabled LPBACK: UARTx Loopback Mode Select bit 1 = Enable Loopback mode 0 = Loopback mode is disabled ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character - requires reception of a Sync field (55h); cleared in hardware upon completion 0 = Baud rate measurement disabled or completed If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 9.4 "Peripheral Pin Select" for more information. This feature is only available for the 16x BRG mode (BRGH = 0).
bit 14 bit 13
bit 12
bit 11
bit 10 bit 9-8
bit 7
bit 6
bit 5
Note 1: 2:
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REGISTER 16-1:
bit 4
UxMODE: UARTx MODE REGISTER (CONTINUED)
RXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is `0' 0 = UxRX Idle state is `1' BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) PDSEL1:PDSEL0: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 9.4 "Peripheral Pin Select" for more information. This feature is only available for the 16x BRG mode (BRGH = 0).
bit 3
bit 2-1
bit 0
Note 1: 2:
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REGISTER 16-2:
R/W-0 UTXISEL1 bit 15 R/W-0 URXISEL1 bit 7 Legend: R = Readable bit -n = Value at POR bit 15,13 C = Clearable bit W = Writable bit `1' = Bit is set HC = Hardware Clearable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 URXISEL0 R/W-0 ADDEN R-1 RIDLE R-0 PERR R-0 FERR R/C-0 OERR R-0 URXDA bit 0
UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0 UTXISEL0 U-0 -- R/W-0 HC UTXBRK R/W-0 UTXEN(2) R-0 UTXBF R-1 TRMT bit 8
R/W-0 UTXINV(1)
UTXISEL1:UTXISEL0: Transmission Interrupt Mode Selection bits 11 = Reserved; do not use 10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR) and as a result, the transmit buffer becomes empty 01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations are completed 00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least one character open in the transmit buffer) UTXINV: IrDA(R) Encoder Transmit Polarity Inversion bit(1) IREN = 0: 1 = UxTX Idle `0' 0 = UxTX Idle `1' IREN = 1: 1 = UxTX Idle `1' 0 = UxTX Idle `0' Unimplemented: Read as `0' UTXBRK: Transmit Break bit 1 = Send Sync Break on next transmission - Start bit, followed by twelve `0' bits, followed by Stop bit; cleared by hardware upon completion 0 = Sync Break transmission disabled or completed UTXEN: Transmit Enable bit(2) 1 = Transmit enabled, UxTX pin controlled by UARTx 0 = Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled by PORT. UTXBF: Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written TRMT: Transmit Shift Register Empty bit (read-only) 1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift Register is not empty, a transmission is in progress or queued Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1). If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 9.4 "Peripheral Pin Select" for more information.
bit 14
bit 12 bit 11
bit 10
bit 9
bit 8
Note 1: 2:
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REGISTER 16-2:
bit 7-6
UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
URXISEL1:URXISEL0: Receive Interrupt Mode Selection bits 11 = Interrupt is set on RSR transfer, making the receive buffer full (i.e., has 4 data characters) 10 = Interrupt is set on RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = Interrupt is set when any character is received and transferred from the RSR to the receive buffer. Receive buffer has one or more characters. ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect. 0 = Address Detect mode disabled RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at the top of the receive FIFO) 0 = Parity error has not been detected FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (character at the top of the receive FIFO) 0 = Framing error has not been detected OERR: Receive Buffer Overrun Error Status bit (clear/read-only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed (clearing a previously set OERR bit (1 0 transition) will reset the receiver buffer and the RSR to the empty state URXDA: Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1). If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 9.4 "Peripheral Pin Select" for more information.
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1: 2:
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NOTES:
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17.0 UNIVERSAL SERIAL BUS WITH ON-THE-GO SUPPORT (USB OTG)
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 27. USB On-The-Go (OTG)". The USB OTG module can function as a USB peripheral device or as a USB host, and may dynamically switch between Device and Host modes under software control. In either mode, the same data paths and buffer descriptors are used for the transmission and reception of data. In discussing USB operation, this section will use a controller-centric nomenclature for describing the direction of the data transfer between the microcontroller and the USB. Rx (Receive) will be used to describe transfers that move data from the USB to the microcontroller, and Tx (Transmit) will be used to describe transfers that move data from the microcontroller to the USB. Table 17-1 shows the relationship between data direction in this nomenclature and the USB tokens exchanged.
Note:
PIC24FJ256GB110 family devices contain a full-speed and low-speed compatible, On-The-Go (OTG) USB Serial Interface Engine (SIE). The OTG capability allows the device to act either as a USB peripheral device or as a USB embedded host with limited host capabilities. The OTG capability allows the device to dynamically switch from device to host operation using OTG's Host Negotiation Protocol (HNP). For more details on OTG operation, refer to the "On-The-Go Supplement to the USB 2.0 Specification", published by the USB-IF. For more details on USB operation, refer to the "Universal Serial Bus Specification", v2.0. The USB OTG module offers these features: * USB functionality in Device and Host modes, and OTG capabilities for application-controlled mode switching * Software-selectable module speeds of full speed (12 Mbps) or low speed (1.5 Mbps, available in Host mode only) * Support for all four USB transfer types: control, interrupt, bulk and isochronous * 16 bidirectional endpoints for a total of 32 unique endpoints * DMA interface for data RAM access * Queues up to sixteen unique endpoint transfers without servicing * Integrated on-chip USB transceiver, with support for off-chip transceivers via a digital interface: * Integrated VBUS generation with on-chip comparators and boost generation, and support of external VBUS comparators and regulators through a digital interface * Configurations for on-chip bus pull-up and pull-down resistors A simplified block diagram of the USB OTG module is shown in Figure 17-1.
TABLE 17-1:
CONTROLLER-CENTRIC DATA DIRECTION FOR USB HOST OR TARGET
Direction Rx OUT or SETUP IN Tx IN OUT or SETUP
USB Mode Device Host
This chapter presents the most basic operations needed to implement USB OTG functionality in an application. A complete and detailed discussion of the USB protocol and its OTG supplement are beyond the scope of this data sheet. It is assumed that the user already has a basic understanding of USB architecture and the latest version of the protocol. Not all steps for proper USB operation (such as device enumeration) are presented here. It is recommended that application developers use an appropriate device driver to implement all of the necessary features. Microchip provides a number of application-specific resources, such as USB firmware and driver support. Refer to www.microchip.com for the latest firmware and driver support.
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FIGURE 17-1: USB OTG MODULE BLOCK DIAGRAM
Full-Speed Pull-up Host Pull-down
48 MHz USB Clock
D+(1)
Transceiver
Registers and Control Interface
D-(1)
Host Pull-down
USBID(1) VMIO(1) VPIO(1) DMH(1) DPH(1) DMLN(1) DPLN(1) RCV(1) USBOEN(1) VBUSON(1)
External Transceiver Interface
USB SIE
System RAM
SRP Charge
VBUS
USB Voltage Comparators
SRP Discharge
VUSB VCMPST1(1) VCMPST2(1) VBUSST(1) VCPCON(1)
Transceiver Power 3.3V
USB 3.3V Regulator
VBUS Boost Assist
Note 1:
Pins are multiplexed with digital I/O and other device features.
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17.1 USB Buffer Descriptors and the BDT
Depending on the endpoint buffering configuration used, there are up to 64 sets of buffer descriptors, for a total of 256 bytes. At a minimum, the BDT must be at least 8 bytes long. This is because the USB specification mandates that every device must have Endpoint 0 with both input and output for initial setup. Endpoint mapping in the BDT is dependent on three variables: * Endpoint number (0 to 15) * Endpoint direction (Rx or Tx) * Ping-pong settings (U1CNFG1<1:0>) Figure 17-2 illustrates how these variables are used to map endpoints in the BDT. In Host mode, only Endpoint 0 buffer descriptors are used. All transfers utilize the Endpoint 0 buffer descriptor and Endpoint Control register (U1EP0). For received packets, the attached device's source endpoint is indicated by the value of ENDPT3:ENDPT0 in the USB status register (U1STAT<7:4>). For transmitted packet, the attached device's destination endpoint is indicated by the value written to the Token register (U1TOK).
Endpoint buffer control is handled through a structure called the Buffer Descriptor Table (BDT). This provides a flexible method for users to construct and control endpoint buffers of various lengths and configurations. The BDT can be located in any available, 512-byte aligned block of data RAM. The BDT Pointer (U1BDTP1) contains the upper address byte of the BDT, and sets the location of the BDT in RAM. The user must set this pointer to indicate the table's location. The BDT is composed of Buffer Descriptors (BDs) which are used to define and control the actual buffers in the USB RAM space. Each BD consists of two, 16-bit "soft" (non-fixed-address) registers, BDnSTAT and BDnADR, where n represents one of the 64 possible BDs (range of 0 to 63). BDnSTAT is the status register for BDn, while BDnADR specifies the starting address for the buffer associated with BDn.
FIGURE 17-2:
PPB1:PPB0 = 00 No Ping-Pong Buffers Total BDT Space: 128 bytes
BDT MAPPING FOR ENDPOINT BUFFERING MODES
PPB1:PPB0 = 01 Ping-Pong Buffer on EP0 OUT Total BDT Space: 132 bytes
EP0 Rx Even Descriptor EP0 Rx Odd Descriptor EP0 Tx Descriptor EP1 Rx Descriptor EP1 Tx Descriptor EP15 Tx Descriptor EP15 Tx Descriptor
PPB1:PPB0 = 10 Ping-Pong Buffers on all EPs Total BDT Space: 256 bytes
EP0 Rx Even Descriptor EP0 Rx Odd Descriptor EP0 Tx Even Descriptor EP0 Tx Odd Descriptor EP1 Rx Even Descriptor EP1 Rx Odd Descriptor EP1 Tx Even Descriptor EP1 Tx Odd Descriptor
PPB1:PPB0 = 11 Ping-Pong Buffers on all other EPs except EP0 Total BDT Space: 248 bytes
EP0 Rx Descriptor EP0 Tx Descriptor EP1 Rx Even Descriptor EP1 Rx Odd Descriptor EP1 Tx Even Descriptor EP1 Tx Odd Descriptor
EP0 Rx Descriptor EP0 Tx Descriptor EP1 Rx Descriptor EP1 Tx Descriptor
EP15 Tx Odd Descriptor
EP15 Tx Odd Descriptor
Note:
Memory area not shown to scale.
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17.1.1 BUFFER OWNERSHIP
Because the buffers and their BDs are shared between the CPU and the USB module, a simple semaphore mechanism is used to distinguish which is allowed to update the BD and associated buffers in memory. This is done by using the UOWN bit as a semaphore to distinguish which is allowed to update the BD and associated buffers in memory. UOWN is the only bit that is shared between the two configurations of BDnSTAT. When UOWN is clear, the BD entry is "owned" by the microcontroller core. When the UOWN bit is set, the BD entry and the buffer memory are "owned" by the USB peripheral. The core should not modify the BD or its corresponding data buffer during this time. Note that the microcontroller core can still read BDnSTAT while the SIE owns the buffer and vice versa. The buffer descriptors have a different meaning based on the source of the register update. Register 17-1 and Register 17-2 show the differences in BDnSTAT depending on its current "ownership". When UOWN is set, the user can no longer depend on the values that were written to the BDs. From this point, the USB module updates the BDs as necessary, overwriting the original BD values. The BDnSTAT register is updated by the SIE with the token PID and the transfer count is updated.
17.1.2
DMA INTERFACE
The USB OTG module uses a dedicated DMA to access both the BDT and the endpoint data buffers. Since part of the address space of the DMA is dedicated to the Buffer Descriptors, a portion of the memory connected to the DMA must comprise a contiguous address space properly mapped for the access by the module.
REGISTER 17-1:
R/W-x UOWN bit 15 R/W-x BC7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15
BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER PROTOTYPE, USB MODE (BD0STAT THROUGH BD63STAT)
R/W-x PID3 R/W-x PID2 R/W-x PID1 R/W-x PID0 R/W-x BC9 R/W-x BC8 bit 8 DTS
R/W-x
R/W-x BC6
R/W-x BC5
R/W-x BC4
R/W-x BC3
R/W-x BC2
R/W-x BC1
R/W-x BC0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
UOWN: USB Own bit 1 = The USB module owns the BD and its corresponding buffer; the CPU must not modify the BD or the buffer DTS: Data Toggle Packet bit 1 = Data 1 packet 0 = Data 0 packet PID3:PID0: Packet Identifier bits (written by the USB module) In Device mode: Represents the PID of the received token during the last transfer. In Host mode: Represents the last returned PID, or the transfer status indicator. BC9:BC0: Byte Count This represents the number of bytes to be transmitted or the maximum number of bytes to be received during a transfer. Upon completion, the byte count is updated by the USB module with the actual number of bytes transmitted or received.
bit 14
bit 13-10
bit 9-0
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REGISTER 17-2:
R/W-x UOWN bit 15 R/W-x BC7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-x BC6 R/W-x BC5 R/W-x BC4 R/W-x BC3 R/W-x BC2 R/W-x BC1
BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER PROTOTYPE, CPU MODE (BD0STAT THROUGH BD63STAT)
R/W-x 0 R/W-x 0 R/W-x DTSEN R/W-x BSTALL R/W-x BC9 R/W-x BC8 bit 8 R/W-x BC0 bit 0
R/W-x DTS(1)
UOWN: USB Own bit 0 = The microcontroller core owns the BD and its corresponding buffer. The USB module ignores all other fields in the BD. DTS: Data Toggle Packet bit(1) 1 = Data 1 packet 0 = Data 0 packet Reserved Function: Maintain as `0' DTSEN: Data Toggle Synchronization Enable bit 1 = Data toggle synchronization is enabled; data packets with incorrect sync value will be ignored 0 = No data toggle synchronization is performed BSTALL: Buffer Stall Enable bit 1 = Buffer STALL enabled; STALL handshake issued if a token is received that would use the BD in the given location (UOWN bit remains set, BD value is unchanged); corresponding EPSTALL bit will get set on any STALL handshake 0 = Buffer STALL disabled BC9:BC0: Byte Count bits This represents the number of bytes to be transmitted or the maximum number of bytes to be received during a transfer. Upon completion, the byte count is updated by the USB module with the actual number of bytes transmitted or received. This bit is ignored unless DTSEN = 1.
bit 14
bit 13-12 bit 11
bit 10
bit 9-0
Note 1:
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17.2 VBUS Voltage Generation
3. When operating as a USB host, either as an A-device in an OTG configuration or as an embedded host, VBUS must be supplied to the attached device. PIC24FJ256GB110 family devices have an internal VBUS boost assist to help generate the required 5V VBUS from the available voltages on the board. Figure 17-3 shows how the internal VBUS components of the USB OTG module work in A-device and B-device configurations. To enable voltage generation: 1. Verify that the USB module is powered (U1PWRC<0> = 1) and that the VBUS discharge is disabled (U1OTGCON<0> = 0). Set the PWM period (U1PWMRRS<7:0>) and duty cycle (U1PWMRRS<15:8>) as required. Select the required polarity of the output signal based on the configuration of the external circuit with the PWMPOL bit (U1PWMCON<9>). Select the desired target voltage using the VBUSCHG bit (U1OTGCON<1>). Enable the PWM counter by setting the CNTEN bit to `1' (U1PWMCON<8>). Enable the PWM module by setting the PWMEN bit to `1' (U1PWMCON<15>). Enable the VBUS generation circuit (U1OTGCON<3> = 1). Note: This section describes the general process for VBUS voltage generation and control. Please refer to the "PIC24F Family Reference Manual" for additional examples.
4. 5. 6. 7.
2.
FIGURE 17-3:
USB VOLTAGE GENERATION AND CONNECTIONS BETWEEN AN A-DEVICE AND A B-DEVICE
PIC24FJ256GB1XX
B-DEVICE 5V BOOST ASSIST
PIC24FJ256GB1XX
A-DEVICE (HOST) 5V BOOST ASSIST(1)
USB SIE
USB SIE
VBUS COMPARATORS RECEPTACLE A PLUG
3.3V REGULATOR
RECEPTACLE
B PLUG
VBUS (5V) D+ DGND ID
VBUS COMPARATORS
3.3V REGULATOR
XCVR GND ID
D+ D-
D+ D-
XCVR GND ID
Note 1:
Additional external components (not shown here) and software configuration are required for a host device to generate VBUS. For more information, refer to the "PIC24F Family Reference Manual".
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17.3 USB Interrupts
17.3.1 CLEARING USB OTG INTERRUPTS
The USB OTG module has many conditions that can be configured to cause an interrupt. All interrupt sources use the same interrupt vector. Figure 17-4 shows the interrupt logic for the USB module. There are two layers of interrupt registers in the USB module. The top level consists of overall USB status interrupts; these are enabled and flagged in the U1IE and U1IR registers, respectively. The second level consists of USB error conditions, which are enabled and flagged in the U1EIR and U1EIE registers. An interrupt condition in any of these triggers a USB Error Interrupt Flag (UERRIF) in the top level. Unlike device level interrupts, the USB OTG interrupt status flags are not freely writable in software. All USB OTG flag bits are implemented as hardware set only bits. Additionally, these bits can only be cleared in software by writing a `1' to their locations (i.e., performing a MOV type instruction). Writing a `0' to a flag bit (i.e., a BCLR instruction) has no effect. Note: Throughout this data sheet, a bit that can only be cleared by writing a `1' to its location is referred to as "Write 1 to clear". In register descriptions, this function is indicated by the descriptor "K".
FIGURE 17-4:
USB OTG INTERRUPT FUNNEL
Top Level (USB Status) Interrupts STALLIF STALLIE ATTACHIF ATTACHIE RESUMEIF RESUMEIE IDLEIF IDLEIE TRNIF TRNIE
Second Level (USB Error) Interrupts BTSEF BTSEE DMAEF DMAEE BTOEF BTOEE DFN8EF DFN8EE CRC16EF CRC16EE CRC5EF (EOFEF) CRC5EE (EOFEE) PIDEF PIDEE SOFIF SOFIE URSTIF (DETACHIF) URSTIE (DETACHIE) Set USB1IF
(UERRIF) UERRIE IDIF IDIE T1MSECIF TIMSECIE LSTATEIF LSTATEIE ACTVIF ACTVIE SESVDIF SESVDIE SESENDIF SESENDIE VBUSVDIF VBUSVDIE
Top Level (USB OTG) Interrupts
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17.4 Device Mode Operation
17.4.3
1. 2. 3. The following section describes how to perform a common Device mode task. In Device mode, USB transfers are performed at the transfer level. The USB module automatically performs the status phase of the transfer.
RECEIVING AN OUT TOKEN IN DEVICE MODE
17.4.1
1.
ENABLING DEVICE MODE
2. 3. 4. 5. 6. 7.
8. 9.
Reset the Ping-Pong Buffer Pointers by setting, then clearing, the Ping-Pong Buffer Reset bit PPBRST (U1CON<1>). Disable all interrupts (U1IE and U1EIE = 00h). Clear any existing interrupt flags by writing FFh to U1IR and U1EIR. Verify that VBUS is present (non OTG devices only). Enable the USB module by setting the USBEN bit (U1CON<0>). Set the OTGEN bit (U1OTGCON<2>) to enable OTG operation. Enable the endpoint zero buffer to receive the first setup packet by setting the EPRXEN and EPHSHK bits for Endpoint 0 (U1EP0<3,0> = 1). Power up the USB module by setting the USBPWR bit (U1PWRC<0>). Enable the D+ pull-up resistor to signal an attach by setting DPPULUP (U1OTGCON<7>).
4.
Attach to a USB host and enumerate as described in Chapter 9 of the USB 2.0 specification. Create a data buffer with the amount of data you are expecting from the host. In the appropriate (EVEN or ODD) Tx BD for the desired endpoint: a) Set up the status register (BDnSTAT) with the correct data toggle (DATA0/1) value and the byte count of the data buffer. b) Set up the address register (BDnADR) with the starting address of the data buffer. c) Set the UOWN bit of the status register to `1'. When the USB module receives an OUT token, it automatically receives the data sent by the host to the buffer. Upon completion, the module updates the status register (BDnSTAT) and sets the Transfer Complete Interrupt Flag, TRNIF (U1IR<3>).
17.5
Host Mode Operation
17.4.2
1. 2. 3.
RECEIVING AN IN TOKEN IN DEVICE MODE
4.
Attach to a USB host and enumerate as described in Chapter 9 of the USB 2.0 specification. Create a data buffer, and populate it with the data to send to the host. In the appropriate (EVEN or ODD) Tx BD for the desired endpoint: a) Set up the status register (BDnSTAT) with the correct data toggle (DATA0/1) value and the byte count of the data buffer. b) Set up the address register (BDnADR) with the starting address of the data buffer. c) Set the UOWN bit of the status register to `1'. When the USB module receives an IN token, it automatically transmits the data in the buffer. Upon completion, the module updates the status register (BDnSTAT) and sets the Transfer Complete Interrupt Flag, TRNIF (U1IR<3>).
The following sections describe how to perform common Host mode tasks. In Host mode, USB transfers are invoked explicitly by the host software. The host software is responsible for the Acknowledge portion of the transfer. Also, all transfers are performed using the Endpoint 0 control register (U1EP0) and buffer descriptors.
17.5.1
1.
ENABLE HOST MODE AND DISCOVER A CONNECTED DEVICE
2.
3.
4. 5.
Enable Host mode by setting U1CON<3> (HOSTEN). This causes the Host mode control bits in other USB OTG registers to become available. Enable the D+ and D- pull-down resistors by setting DPPULDWN and DMPULDWN (U1OTGCON<5:4>). Disable the D+ and Dpull-up resistors by clearing DPPULUP and DMPULUP (U1OTGCON<7:6>). At this point, SOF generation begins with the SOF counter loaded with 12,000. Eliminate noise on the USB by clearing the SOFEN bit (U1CON<0>) to disable Start-Of-Frame packet generation. Enable the device attached interrupt by setting ATTACHIE (U1IE<6>). Wait for the device attached interrupt (U1IR<6> = 1). This is signaled by the USB device changing the state of D+ or D- from `0' to `1' (SE0 to J state). After it occurs, wait 100 ms for the device power to stabilize.
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Check the state of the JSTATE and SE0 bits in U1CON. If the JSTATE bit (U1CON<7>) is `0', the connecting device is low speed. If the connecting device is low speed, set the low LSPDEN and LSPD bits (U1ADDR<7> and U1EP0<7>) to enable low-speed operation. 7. Reset the USB device by setting the RESET bit (U1CON<4>) for at least 50 ms, sending Reset signaling on the bus. After 50 ms, terminate the Reset by clearing RESET. 8. To keep the connected device from going into suspend, enable SOF packet generation to keep by setting the SOFEN bit. 9. Wait 10 ms for the device to recover from Reset. 10. Perform enumeration as described by Chapter 9 of the USB 2.0 specification. 6. 7. To initiate the data phase of the setup transaction (i.e., get the data for the GET DEVICE descriptor command), set up a buffer in memory to store the received data. 8. Initialize the current (EVEN or ODD) Rx or Tx (Rx for IN, Tx for OUT) EP0 BD to transfer the data. a) Write C040h to BD0STAT. This sets the UOWN, configures Data Toggle (DTS) to DATA1, and sets the byte count to the length of the data buffer (64 or 40h, in this case). b) Set BD0ADR to the starting address of the data buffer. 9. Write the token register with the appropriate IN or OUT token to Endpoint 0, the target device's default control pipe (e.g., write 90h to U1TOK for an IN token for a GET DEVICE DESCRIPTOR command). This initiates an IN token on the bus followed by a data packet from the device to the host. When the data packet completes, the BD0STAT is written and a transfer done interrupt is asserted (the TRNIF flag is set). For control transfers with a single packet data phase, this completes the data phase of the setup transaction as referenced in chapter 9 of the USB specification. If more data needs to be transferred, return to step 8. 10. To initiate the status phase of the setup transaction, set up a buffer in memory to receive or send the zero length status phase data packet. 11. Initialize the current (even or odd) Tx EP0 BD to transfer the status data.: a) Set the BDT buffer address field to the start address of the data buffer b) Write 8000h to BD0STAT (set UOWN bit, configure DTS to DATA0, and set byte count to 0). 12. Write the Token register with the appropriate IN or OUT token to Endpoint 0, the target device's default control pipe (e.g., write 01h to U1TOK for an OUT token for a GET DEVICE DESCRIPTOR command). This initiates an OUT token on the bus followed by a zero length data packet from the host to the device. When the data packet completes, the BD is updated with the handshake from the device, and a transfer done interrupt is asserted (the TRNIF flag is set). This completes the status phase of the setup transaction as described in chapter 9 of the USB specification. Note: Only one control transaction can be performed per frame.
17.5.2
COMPLETE A CONTROL TRANSACTION TO A CONNECTED DEVICE
1.
2.
3.
4.
5.
6.
Follow the procedure described in Section 17.5.1 "Enable Host Mode and Discover a Connected Device" to discover a device. Set up the Endpoint Control register for bidirectional control transfers by writing 0Dh to U1EP0 (this sets the EPCONDIS, EPTXEN, and EPHSHK bits). Place a copy of the device framework setup command in a memory buffer. See Chapter 9 of the USB 2.0 specification for information on the device framework command set. Initialize the buffer descriptor (BD) for the current (EVEN or ODD) Tx EP0, to transfer the eight bytes of command data for a device framework command (i.e., a GET DEVICE DESCRIPTOR): a) Set the BD data buffer address (BD0ADR) to the starting address of the 8-byte memory buffer containing the command. b) Write 8008h to BD0STAT (this sets the UOWN bit, and sets a byte count of 8). Set the USB device address of the target device in the address register (U1ADDR<6:0>). After a USB bus Reset, the device USB address will be zero. After enumeration, it will be set to another value between 1 and 127. Write D0h to U1TOK; this is a SETUP token to Endpoint 0, the target device's default control pipe. This initiates a SETUP token on the bus, followed by a data packet. The device handshake is returned in the PID field of BD0STAT after the packets are complete. When the USB module updates BD0STAT, a transfer done interrupt is asserted (the TRNIF flag is set). This completes the setup phase of the setup transaction as referenced in chapter 9 of the USB specification.
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17.5.3
1.
SEND A FULL-SPEED BULK DATA TRANSFER TO A TARGET DEVICE
17.6
17.6.1
OTG Operation
SESSION REQUEST PROTOCOL (SRP)
2.
3. 4. 5.
6.
7.
Follow the procedure described in Section 17.5.1 "Enable Host Mode and Discover a Connected Device" and Section 17.5.2 "Complete a Control Transaction to a Connected Device" to discover and configure a device. To enable transmit and receive transfers with handshaking enabled, write 1Dh to U1EP0. If the target device is a low-speed device, also set the LSPD bit (U1EP0<7>). If you want the hardware to automatically retry indefinitely if the target device asserts a NAK on the transfer, clear the Retry Disable bit, RETRYDIS (U1EP0<6>). Set up the BD for the current (EVEN or ODD) Tx EP0 to transfer up to 64 bytes. Set the USB device address of the target device in the address register (U1ADDR<6:0>). Write an OUT token to the desired endpoint to U1TOK. This triggers the module's transmit state machines to begin transmitting the token and the data. Wait for the Transfer Done Interrupt Flag, TRNIF. This indicates that the BD has been released back to the microprocessor, and the transfer has completed. If the retry disable bit is set, the handshake (ACK, NAK, STALL or ERROR (0Fh)) is returned in the BD PID field. If a STALL interrupt occurs, the pending packet must be dequeued and the error condition in the target device cleared. If a detach interrupt occurs (SE0 for more than 2.5 s), then the target has detached (U1IR<0> is set). Once the transfer done interrupt occurs (TRNIF is set), the BD can be examined and the next data packet queued by returning to step 2. Note: USB speed, transceiver and pull-ups should only be configured during the module setup phase. It is not recommended to change these settings while the module is enabled.
An OTG A-device may decide to power down the VBUS supply when it is not using the USB link through the Session Request Protocol (SRP). Software may do this by clearing VBUSON (U1OTGCON<3>). When the VBUS supply is powered down, the A-device is said to have ended a USB session. An OTG A-device or Embedded Host may re-power the VBUS supply at any time (initiate a new session). An OTG B-device may also request that the OTG A-device re-power the VBUS supply (initiate a new session). This is accomplished via Session Request Protocol (SRP). Prior to requesting a new session, the B-device must first check that the previous session has definitely ended. To do this, the B-device must check for two conditions: 1. VBUS supply is below the Session Valid voltage, and 2. Both D+ and D- have been low for at least 2 ms. The B-device will be notified of condition 1 by the SESENDIF (U1OTGIR<2>) interrupt. Software will have to manually check for condition 2. Note: When the A-device powers down the VBUS supply, the B-device must disconnect its pull-up resistor from power. If the device is self-powered, it can do this by clearing DPPULUP (U1OTGCON<7>) and DMPULUP (U1OTGCON<6>).
The B-device may aid in achieving condition 1 by discharging the VBUS supply through a resistor. Software may do this by setting VBUSDIS (U1OTGCON<0>). After these initial conditions are met, the B-device may begin requesting the new session. The B-device begins by pulsing the D+ data line. Software should do this by setting DPPULUP (U1OTGCON<7>). The data line should be held high for 5 to 10 ms. The B-device then proceeds by pulsing the VBUS supply. Software should do this by setting VBUSCHG (UTOGCTRL<1>). When an A-device detects SRP signaling (either via the ATTACHIF (U1IR<6>) interrupt or via the SESVDIF (U1OTGIR<3>) interrupt), the A-device must restore the VBUS supply by setting VBUSON (U1OTGCON<3>). The B-device should not monitor the state of the VBUS supply while performing VBUS supply pulsing. When the B-device does detect that the VBUS supply has been restored (via the SESVDIF (U1OTGIR<3>) interrupt), the B-device must re-connect to the USB link by pulling up D+ or D- (via the DPPULUP or DMPULUP). The A-device must complete the SRP by driving USB Reset signaling.
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17.6.2 HOST NEGOTIATION PROTOCOL (HNP)
17.7
USB OTG Module Registers
In USB OTG applications, a Dual Role Device (DRD) is a device that is capable of being either a host or a peripheral. Any OTG DRD must support Host Negotiation Protocol (HNP). HNP allows an OTG B-device to temporarily become the USB host. The A-device must first enable the B-device to follow HNP. Refer to the On-The-Go Supplement to the USB 2.0 Specification for more information regarding HNP. HNP may only be initiated at full speed. After being enabled for HNP by the A-device, the B-device requests being the host any time that the USB link is in Suspend state, by simply indicating a disconnect. This can be done in software by clearing DPPULUP and DMPULUP. When the A-device detects the disconnect condition (via the URSTIF (U1IR<0>) interrupt), the A-device may allow the B-device to take over as Host. The A-device does this by signaling connect as a full-speed function. Software may accomplish this by setting DPPULUP. If the A-device responds instead with resume signaling, the A-device remains as host. When the B-device detects the connect condition (via ATTACHIF (U1IR<6>), the B-device becomes host. The B-device drives Reset signaling prior to using the bus. When the B-device has finished in its role as Host, it stops all bus activity and turns on its D+ pull-up resistor by setting DPPULUP. When the A-device detects a suspend condition (Idle for 3 ms), the A-device turns off its D+ pull-up. The A-device may also power-down VBUS supply to end the session. When the A-device detects the connect condition (via ATTACHIF), the A-device resumes host operation, and drives Reset signaling.
There are a total of 37 memory mapped registers associated with the USB OTG module. They can be divided into four general categories: * * * * USB OTG Module Control (12) USB Interrupt (7) USB Endpoint Management (16) USB VBUS Power Control (2)
This total does not include the (up to) 128 BD registers in the BDT. Their prototypes, described in Register 17-1 and Register 17-2, are shown separately in Section 17.1 "USB Buffer Descriptors and the BDT". With the exception U1PWMCON and U1PWMRRS, all USB OTG registers are implemented in the Least Significant Byte of the register. Bits in the upper byte are unimplemented, and have no function. Note that some registers are instantiated only in Host mode, while other registers have different bit instantiations and functions in Device and Host modes. Registers described in the following sections are those that have bits with specific control and configuration features. The following registers are used for data or address values only: * U1BDTP1: Specifies the 256-word page in data RAM used for the BDT; 8-bit value with bit 0 fixed as `0' for boundary alignment * U1FRML and U1FRMH: Contains the 11-bit byte counter for the current data frame * U1PWMRRS: Contains the 8-bit value for PWM duty cycle (bits 15:8) and PWM period (bits 7:0) for the VBUS boost assist PWM module.
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17.7.1 USB OTG MODULE CONTROL REGISTERS U1OTGSTAT: USB OTG STATUS REGISTER (HOST MODE ONLY)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- R-0, HSC LSTATE U-0 -- R-0, HSC SESVD R-0, HSC SESEND U-0 -- R-0, HSC VBUSVD bit 0 U = Unimplemented bit, read as `0' W = Writable bit `1' = Bit is set HSC = Hardware Settable/Clearable bit `0' = Bit is cleared x = Bit is unknown
REGISTER 17-3:
U-0 -- bit 15 R-0, HSC ID bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7
Unimplemented: Read as `0' ID: ID Pin State Indicator bit 1 = No plug is attached, or a type B cable has been plugged into the USB receptacle 0 = A type A plug has been plugged into the USB receptacle Unimplemented: Read as `0' LSTATE: Line State Stable Indicator bit 1 = The USB line state (as defined by SE0 and JSTATE) has been stable for the previous 1 ms 0 = The USB line state has NOT been stable for the previous 1 ms Unimplemented: Read as `0' SESVD: Session Valid Indicator bit 1 = The VBUS voltage is above VA_SESS_VLD (as defined in the USB OTG Specification) on the A or B-device 0 = The VBUS voltage is below VA_SESS_VLD on the A or B-device SESEND: B-Session End Indicator bit 1 = The VBUS voltage is below VB_SESS_END (as defined in the USB OTG Specification) on the B-device 0 = The VBUS voltage is above VB_SESS_END on the B-device Unimplemented: Read as `0' VBUSVD: A-VBUS Valid Indicator bit 1 = The VBUS voltage is above VA_VBUS_VLD (as defined in the USB OTG Specification) on the A-device 0 = The VBUS voltage is below VA_VBUS_VLD on the A-device
bit 6 bit 5
bit 4 bit 3
bit 2
bit 1 bit 0
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REGISTER 17-4:
U-0 -- bit 15 R/W-0 DPPULUP bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 DMPULUP R/W-0 R/W-0 R/W-0 VBUSON(1) R/W-0 OTGEN(1) R/W-0 U-0 --
U1OTGCON: USB ON-THE-GO CONTROL REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 bit 0
DPPULDWN(1) DMPULDWN(1)
VBUSCHG(1) VBUSDIS(1)
Unimplemented: Read as `0' DPPULUP: D+ Pull-Up Enable bit 1 = D+ data line pull-up resistor enabled 0 = D+ data line pull-up resistor disabled DMPULUP: D- Pull-Up Enable bit 1 = D- data line pull-up resistor enabled 0 = D- data line pull-up resistor disabled DPPULDWN: D+ Pull-Down Enable bit(1) 1 = D+ data line pull-down resistor enabled 0 = D+ data line pull-down resistor disabled DMPULDWN: D- Pull-Down Enable bit(1) 1 = D- data line pull-down resistor enabled 0 = D- data line pull-down resistor disabled VBUSON: VBUS Power-on bit(1) 1 = VBUS line powered 0 = VBUS line not powered OTGEN: OTG Features Enable bit(1) 1 = USB OTG enabled; all D+/D- pull-ups and pull-downs bits are enabled 0 = USB OTG disabled; D+/D- pull-ups and pull-downs are controlled in hardware by the settings of the HOSTEN and USBEN bits (U1CON<3,0>) VBUSCHG: VBUS Charge Select bit(1) 1 = VBUS line set to charge to 3.3V 0 = VBUS line set to charge to 5V VBUSDIS: VBUS Discharge Enable bit(1) 1 = VBUS line discharged through a resistor 0 = VBUS line not discharged These bits are only used in Host mode; do not use in Device mode.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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REGISTER 17-5:
U-0 -- bit 15 R/W-0, HS UACTPND bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 HS = Hardware Settable bit W = Writable bit `1' = Bit is set HC = Hardware Clearable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 USLPGRD U-0 -- U-0 -- R/W-0, HC USUSPND --
U1PWRC: USB POWER CONTROL REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 USBPWR bit 0
U-0
Unimplemented: Read as `0' UACTPND: USB Activity Pending bit 1 = Module should not be suspended at the moment (requires USLPGRD bit to be set) 0 = Module may be suspended or powered down Unimplemented: Read as `0' USLPGRD: Sleep/Suspend Guard bit 1 = Indicate to the USB module that it is about to be suspended or powered down 0 = No suspend Unimplemented: Read as `0' USUSPND: USB Suspend Mode Enable bit 1 = USB OTG module is in Suspend mode; USB clock is gated and the transceiver is placed in a low-power state 0 = Normal USB OTG operation USBPWR: USB Operation Enable bit 1 = USB OTG module is enabled 0 = USB OTG module is disabled(1) Do not clear this bit unless the HOSTEN, USBEN and OTGEN bits (U1CON<3,0> and U1OTGCON<2>) are all cleared.
bit 6-5 bit 4
bit 3-2 bit 1
bit 0
Note 1:
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REGISTER 17-6:
U-0 -- bit 15 R-0, HSC ENDPT3 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' HSC = Hardware Settable/Clearable bit `0' = Bit is cleared x = Bit is unknown R-0, HSC ENDPT2 R-0, HSC ENDPT1 R-0, HSC ENDPT0 R-0, HSC DIR R-0, HSC PPBI(1) U-0 -- U-0 -- bit 0
U1STAT: USB STATUS REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8
Unimplemented: Read as `0' ENDPT3:ENDPT0: Number of the Last Endpoint Activity bits (Represents the number of the BDT updated by the last USB transfer). 1111 = Endpoint 15 1110 = Endpoint 14 .... 0001 = Endpoint 1 0000 = Endpoint 0 DIR: Last BD Direction Indicator bit 1 = The last transaction was a transmit transfer (Tx) 0 = The last transaction was a receive transfer (Rx) PPBI: Ping-Pong BD Pointer Indicator bit(1) 1 = The last transaction was to the ODD BD bank 0 = The last transaction was to the EVEN BD bank Unimplemented: Read as `0' This bit is only valid for endpoints with available EVEN and ODD BD registers.
bit 3
bit 2
bit 1-0 Note 1:
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REGISTER 17-7:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' HSC = Hardware Settable/Clearable bit `0' = Bit is cleared x = Bit is unknown R-x, HSC SE0 R/W-0 PKTDIS U-0 -- R/W-0 HOSTEN R/W-0 RESUME R/W-0 PPBRST
U1CON: USB CONTROL REGISTER (DEVICE MODE)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 USBEN bit 0
Unimplemented: Read as `0' SE0: Live Single-Ended Zero Flag bit 1 = Single-ended zero active on the USB bus 0 = No single-ended zero detected PKTDIS: Packet Transfer Disable bit 1 = SIE token and packet processing disabled; automatically set when a SETUP token is received 0 = SIE token and packet processing enabled Unimplemented: Read as `0' HOSTEN: Host Mode Enable bit 1 = USB host capability enabled; pull-downs on D+ and D- are activated in hardware 0 = USB host capability disabled RESUME: Resume Signaling Enable bit 1 = Resume signaling activated 0 = Resume signaling disabled PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Ping-Pong Buffer Pointers to the EVEN BD banks 0 = Ping-Pong Buffer Pointers not reset USBEN: USB Module Enable bit 1 = USB module and supporting circuitry enabled (device attached); D+ pull-up is activated in hardware 0 = USB module and supporting circuitry disabled (device detached)
bit 5
bit 4 bit 3
bit 2
bit 1
bit 0
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REGISTER 17-8:
U-0 -- bit 15 R-x, HSC JSTATE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' HSC = Hardware Settable/Clearable bit `0' = Bit is cleared x = Bit is unknown R-x, HSC SE0 R/W-0 TOKBUSY R/W-0 RESET R/W-0 HOSTEN R/W-0 RESUME R/W-0 PPBRST
U1CON: USB CONTROL REGISTER (HOST MODE ONLY)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 SOFEN bit 0
Unimplemented: Read as `0' JSTATE: Live Differential Receiver J State Flag bit 1 = J state (differential `0' in low speed, differential `1' in full speed) detected on the USB 0 = No J state detected SE0: Live Single-Ended Zero Flag bit 1 = Single-ended zero active on the USB bus 0 = No single-ended zero detected TOKBUSY: Token Busy Status bit 1 = Token being executed by the USB module in On-The-Go state 0 = No token being executed RESET: Module Reset bit 1 = USB Reset has been generated; for software Reset, application must set this bit for 10 ms, then clear it 0 = USB Reset terminated HOSTEN: Host Mode Enable bit 1 = USB host capability enabled; pull-downs on D+ and D- are activated in hardware 0 = USB host capability disabled RESUME: Resume Signaling Enable bit 1 = Resume signaling activated; software must set bit for 10 ms and then clear to enable remote wake-up 0 = Resume signaling disabled PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Ping-Pong Buffer Pointers to the EVEN BD banks 0 = Ping-Pong Buffer Pointers not reset SOFEN: Start-Of-Frame Enable bit 1 = Start-Of-Frame token sent every one 1 millisecond 0 = Start-Of-Frame token disabled
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 17-9:
U-0 -- bit 15 R/W-0 LSPDEN bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
(1)
U1ADDR: USB ADDRESS REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 R/W-0 ADDR5 R/W-0 ADDR4 R/W-0 ADDR3 R/W-0 ADDR2 R/W-0 ADDR1 R/W-0 ADDR0 bit 0
ADDR6
Unimplemented: Read as `0' LSPDEN: Low-Speed Enable Indicator bit(1) 1 = USB module operates at low speed 0 = USB module operates at full speed ADDR6:ADDR0: USB Device Address bits Host mode only. In Device mode, this bit is unimplemented and read as `0'.
bit 6-0 Note 1:
REGISTER 17-10: U1TOK: USB TOKEN REGISTER (HOST MODE ONLY)
U-0 -- bit 15 R/W-0 PID3 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 PID2 R/W-0 PID1 R/W-0 PID0 R/W-0 EP3 R/W-0 EP2 R/W-0 EP1 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 EP0 bit 0
Unimplemented: Read as `0' PID3:PID0: Token Type Identifier bits 1101 = SETUP (TX) token type transaction(1) 1001 = IN (RX) token type transaction(1) 0001 = OUT (TX) token type transaction(1) EP3:EP0: Token Command Endpoint Address bits This value must specify a valid endpoint on the attached device. All other combinations are reserved and are not to be used.
bit 3-0
Note 1:
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REGISTER 17-11:
U-0 -- bit 15 R/W-0 CNT7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
U1SOF: USB OTG START-OF-TOKEN THRESHOLD REGISTER (HOST MODE ONLY)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8
R/W-0 CNT6
R/W-0 CNT5
R/W-0 CNT4
R/W-0 CNT3
R/W-0 CNT2
R/W-0 CNT1
R/W-0 CNT0 bit 0
Unimplemented: Read as `0' CNT7:CNT0: Start-Of-Frame Size bits; Value represents 10 + (packet size of n bytes). For example: 0100 1010 = 64-byte packet 0010 1010 = 32-byte packet 0001 0010 = 8-byte packet
REGISTER 17-12: U1CNFG1: USB CONFIGURATION REGISTER 1
U-0 -- bit 15 R/W-0 UTEYE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 R/W-0 UOEMON(1) U-0 -- R/W-0 USBSIDL U-0 -- U-0 -- R/W-0 PPB1 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 PPB0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' UTEYE: USB Eye Pattern Test Enable bit 1 = Eye pattern test enabled 0 = Eye pattern test disabled UOEMON: USB OE Monitor Enable bit(1) 1 = OE signal active; it indicates intervals during which the D+/D- lines are driving 0 = OE signal inactive Unimplemented: Read as `0' USBSIDL: USB OTG Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' PPB1:PPB0: Ping-Pong Buffers Configuration bit 11 = EVEN/ODD ping-pong buffers enabled for Endpoints 1 to 15 10 = EVEN/ODD ping-pong buffers enabled for all endpoints 01 = EVEN/ODD ping-pong buffer enabled for OUT Endpoint 0 00 = EVEN/ODD ping-pong buffers disabled This bit is only active when the UTRDIS bit (U1CNFG2<0>) is set.
bit 6
bit 5 bit 4
bit 3-2 bit 1-0
Note 1:
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REGISTER 17-13: U1CNFG2: USB CONFIGURATION REGISTER 2
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-5 bit 4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 PUVBUS R/W-0 EXTI2CEN R/W-0 UVBUSDIS
(1)
U-0 --
U-0 --
U-0 --
U-0 --
U-0 --
U-0 --
U-0 -- bit 8
R/W-0 UVCMPDIS
(1)
R/W-0 UTRDIS(1) bit 0
Unimplemented: Read as `0' PUVBUS: VBUS Pull-up Enable bit 1 = Pull-up on VBUS pin enabled 0 = Pull-up on VBUS pin disabled EXTI2CEN: I2CTM Interface For External Module Control Enable bit 1 = External module(s) controlled via I2C interface 0 = External module(s) controller via dedicated pins UVBUSDIS: On-Chip 5V Boost Regulator Builder Disable bit(1) 1 = On-chip boost regulator builder disabled; digital output control interface enabled 0 = On-chip boost regulator builder active UVCMPDIS: On-Chip VBUS Comparator Disable bit(1) 1 = On-chip charge VBUS comparator disabled; digital input status interface enabled 0 = On-chip charge VBUS comparator active UTRDIS: On-Chip Transceiver Disable bit(1) 1 = On-chip transceiver and VBUS detection disabled; digital transceiver interface enabled 0 = On-chip transceiver and VBUS detection active Never change these bits while the USBPWR bit is set (U1PWRC<0> = 1).
bit 3
bit 2
bit 1
bit 0
Note 1:
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17.7.2 USB INTERRUPT REGISTERS REGISTER 17-14: U1OTGIR: USB OTG INTERRUPT STATUS REGISTER (HOST MODE ONLY)
U-0 -- bit 15 R/K-0, HS IDIF bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 K = Write `1' to clear bit `1' = Bit is set U = Unimplemented bit, read as `0' HS = Hardware Settable bit `0' = Bit is cleared x = Bit is unknown R/K-0, HS T1MSECIF R/K-0, HS LSTATEIF R/K-0, HS ACTVIF R/K-0, HS SESVDIF R/K-0, HS SESENDIF U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/K-0, HS VBUSVDIF bit 0
Unimplemented: Read as `0' IDIF: ID State Change Indicator bit 1 = Change in ID state detected 0 = No ID state change T1MSECIF: 1 Millisecond Timer bit 1 = The 1 millisecond timer has expired 0 = The 1 millisecond timer has not expired LSTATEIF: Line State Stable Indicator bit 1 = USB line state (as defined by the SE0 and JSTATE bits) has been stable for 1 ms, but different from last time 0 = USB line state has not been stable for 1 ms ACTVIF: Bus Activity Indicator bit 1 = Activity on the D+/D- lines or VBUS detected 0 = No activity on the D+/D- lines or VBUS detected SESVDIF: Session Valid Change Indicator bit 1 = VBUS has crossed VA_SESS_END (as defined in the USB OTG Specification)(1) 0 = VBUS has not crossed VA_SESS_END SESENDIF: B-Device VBUS Change Indicator bit 1 = VBUS change on B-device detected; VBUS has crossed VB_SESS_END (as defined in the USB OTG Specification)(1) 0 = VBUS has not crossed VA_SESS_END Unimplemented: Read as `0' VBUSVDIF A-Device VBUS Change Indicator bit 1 = VBUS change on A-device detected; VBUS has crossed VA_VBUS_VLD (as defined in the USB OTG Specification)(1) 0 = No VBUS change on A-device detected VBUS threshold crossings may be either rising or falling.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1 bit 0
Note 1:
Note:
Individual bits can only be cleared by writing a `1' to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared.
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REGISTER 17-15: U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER (HOST MODE ONLY)
U-0 -- bit 15 R/W-0 IDIE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 T1MSECIE R/W-0 LSTATEIE R/W-0 ACTVIE R/W-0 SESVDIE R/W-0 SESENDIE U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 VBUSVDIE bit 0
Unimplemented: Read as `0' IDIE: ID Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled T1MSECIE: 1 Millisecond Timer Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled LSTATEIE: Line State Stable Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled ACTVIE: Bus Activity Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled SESVDIE: Session Valid Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled SESENDIE: B-Device Session End Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled Unimplemented: Read as `0' VBUSVDIE: A-Device VBUS Valid Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1 bit 0
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REGISTER 17-16: U1IR: USB INTERRUPT STATUS REGISTER (DEVICE MODE ONLY)
U-0 -- bit 15 R/K-0, HS STALLIF bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 K = Write `1' to clear bit `1' = Bit is set U = Unimplemented bit, read as `0' HS = Hardware Settable bit `0' = Bit is cleared x = Bit is unknown U-0 -- R/K-0, HS RESUMEIF R/K-0, HS IDLEIF R/K-0, HS TRNIF R/K-0, HS SOFIF R-0 UERRIF U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/K-0, HS URSTIF bit 0
Unimplemented: Read as `0' STALLIF: STALL Handshake Interrupt bit 1 = A STALL handshake was sent by the peripheral during the handshake phase of the transaction in Device mode 0 = A STALL handshake has not been sent Unimplemented: Read as `0' RESUMEIF: Resume Interrupt bit 1 = A K-state is observed on the D+ or D- pin for 2.5 s (differential `1' for low speed, differential `0' for full speed) 0 = No K-state observed IDLEIF: Idle Detect Interrupt bit 1 = Idle condition detected (constant Idle state of 3 ms or more) 0 = No Idle condition detected TRNIF: Token Processing Complete Interrupt bit 1 = Processing of current token is complete; read U1STAT register for endpoint information 0 = Processing of current token not complete; clear U1STAT register or load next token from STAT (clearing this bit causes the STAT FIFO to advance) SOFIF: Start-Of-Frame Token Interrupt bit 1 = A Start-Of-Frame token received by the peripheral or the Start-Of-Frame threshold reached by the host 0 = No Start-Of-Frame token received or threshold reached UERRIF: USB Error Condition Interrupt bit (read-only) 1 = An unmasked error condition has occurred; only error states enabled in the U1EIE register can set this bit 0 = No unmasked error condition has occurred URSTIF: USB Reset Interrupt bit 1 = Valid USB Reset has occurred for at least 2.5 s; Reset state must be cleared before this bit can be reasserted 0 = No USB Reset has occurred. Individual bits can only be cleared by writing a `1' to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. Individual bits can only be cleared by writing a `1' to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared.
bit 6 bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note:
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Preliminary
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REGISTER 17-17: U1IR: USB INTERRUPT STATUS REGISTER (HOST MODE ONLY)
U-0 -- bit 15 R/K-0, HS STALLIF bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 K = Write `1' to clear bit `1' = Bit is set U = Unimplemented bit, read as `0' HS = Hardware Settable bit `0' = Bit is cleared x = Bit is unknown R/K-0, HS ATTACHIF R/K-0, HS RESUMEIF R/K-0, HS IDLEIF R/K-0, HS TRNIF R/K-0, HS SOFIF R-0 UERRIF U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/K-0, HS DETACHIF bit 0
Unimplemented: Read as `0' STALLIF: STALL Handshake Interrupt bit 1 = A STALL handshake was sent by the peripheral device during the handshake phase of the transaction in Device mode 0 = A STALL handshake has not been sent ATTACHIF: Peripheral Attach Interrupt bit 1 = A peripheral attachment has been detected by the module; set if the bus state is not SE0 and there has been no bus activity for 2.5 s 0 = No peripheral attachement detected RESUMEIF: Resume Interrupt bit 1 = A K-state is observed on the D+ or D- pin for 2.5 s (differential `1' for low speed, differential `0' for full speed) 0 = No K-state observed IDLEIF: Idle Detect Interrupt bit 1 = Idle condition detected (constant Idle state of 3 ms or more) 0 = No Idle condition detected TRNIF: Token Processing Complete Interrupt bit 1 = Processing of current token is complete; read U1STAT register for endpoint information 0 = Processing of current token not complete; clear U1STAT register or load next token from U1STAT SOFIF: Start-Of-Frame Token Interrupt bit 1 = A Start-Of-Frame token received by the peripheral or the Start-Of-Frame threshold reached by the host 0 = No Start-Of-Frame token received or threshold reached UERRIF: USB Error Condition Interrupt bit 1 = An unmasked error condition has occurred; only error states enabled in the U1EIE register can set this bit 0 = No unmasked error condition has occurred DETACHIF: Detach Interrupt bit 1 = A peripheral detachment has been detected by the module; Reset state must be cleared before this bit can be reasserted 0 = No peripheral detachment detected. Individual bits can only be cleared by writing a `1' to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. Individual bits can only be cleared by writing a `1' to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note:
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REGISTER 17-18: U1IE: USB INTERRUPT ENABLE REGISTER (ALL USB MODES)
U-0 -- bit 15 R/W-0 STALLIE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 ATTACHIE
(1)
U-0 --
U-0 --
U-0 --
U-0 --
U-0 --
U-0 --
U-0 -- bit 8
R/W-0 RESUMEIE
R/W-0 IDLEIE
R/W-0 TRNIE
R/W-0 SOFIE
R/W-0 UERRIE
R/W-0 URSTIE DETACHIE bit 0
Unimplemented: Read as `0' STALLIE: STALL Handshake Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled ATTACHIE: Peripheral Attach Interrupt bit (Host mode only)(1) 1 = Interrupt enabled 0 = Interrupt disabled RESUMEIE: Resume Interrupt bit 1 = Interrupt enabled 0 = Interrupt disabled IDLEIE: Idle Detect Interrupt bit 1 = Interrupt enabled 0 = Interrupt disabled TRNIE: Token Processing Complete Interrupt bit 1 = Interrupt enabled 0 = Interrupt disabled SOFIE: Start-of-Frame Token Interrupt bit 1 = Interrupt enabled 0 = Interrupt disabled UERRIE: USB Error Condition Interrupt bit 1 = Interrupt enabled 0 = Interrupt disabled URSTIE or DETACHIE: USB Reset Interrupt (Device mode) or USB Detach Interrupt (Host mode) Enable bit 1 = Interrupt enabled 0 = Interrupt disabled Unimplemented in Device mode, read as `0'.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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REGISTER 17-19: U1EIR: USB ERROR INTERRUPT STATUS REGISTER
U-0 -- bit 15 R/K-0, HS BTSEF bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 K = Write `1' to clear bit `1' = Bit is set U = Unimplemented bit, read as `0' HS = Hardware Settable bit `0' = Bit is cleared x = Bit is unknown U-0 -- R/K-0, HS DMAEF R/K-0, HS BTOEF R/K-0, HS DFN8EF R/K-0, HS CRC16EF R/K-0, HS CRC5EF EOFEF U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/K-0, HS PIDEF bit 0
Unimplemented: Read as `0' BTSEF: Bit Stuff Error Flag bit 1 = Bit stuff error has been detected 0 = No bit stuff error Unimplemented: Read as `0' DMAEF: DMA Error Flag bit 1 = A USB DMA error condition detected; the data size indicated by the BD byte count field is less than the number of received bytes. The received data is truncated. 0 = No DMA error BTOEF: Bus Turnaround Time-out Error Flag bit 1 = Bus turnaround time-out has occurred 0 = No bus turnaround time-out DFN8EF: Data Field Size Error Flag bit 1 = Data field was not an integral number of bytes 0 = Data field was an integral number of bytes CRC16EF: CRC16 Failure Flag bit 1 = CRC16 failed 0 = CRC16 passed For Device mode: CRC5EF: CRC5 Host Error Flag bit 1 = Token packet rejected due to CRC5 error 0 = Token packet accepted (no CRC5 error) For Host mode: EOFEF: End-Of-Frame Error Flag bit 1 = End-Of-Frame error has occurred 0 = End-Of-Frame interrupt disabled PIDEF: PID Check Failure Flag bit 1 = PID check failed 0 = PID check passed. Individual bits can only be cleared by writing a `1' to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared.
bit 6 bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note:
Individual bits can only be cleared by writing a `1' to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared.
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REGISTER 17-20: U1EIE: USB ERROR INTERRUPT ENABLE REGISTER
U-0 -- bit 15 R/W-0 BTSEE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 DMAEE R/W-0 BTOEE R/W-0 DFN8EE R/W-0 CRC16EE R/W-0 CRC5EE EOFEE U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 PIDEE bit 0
Unimplemented: Read as `0' BTSEE: Bit Stuff Error Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled Unimplemented: Read as `0' DMAEE: DMA Error Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled DFN8EE: Data Field Size Error Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled CRC16EE: CRC16 Failure Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled For Device mode: CRC5EE: CRC5 Host Error Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled For Host mode: EOFEE: End-of-Frame Error interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled PIDEE: PID Check Failure Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled
bit 6 bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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17.7.3 USB ENDPOINT MANAGEMENT REGISTERS REGISTER 17-21: U1EPn: USB ENDPOINT CONTROL REGISTERS (n = 0 TO 15)
U-0 -- bit 15 R/W-0 LSPD(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 RETRYDIS(1) U-0 -- R/W-0 EPCONDIS R/W-0 EPRXEN R/W-0 EPTXEN R/W-0 EPSTALL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 EPHSHK bit 0
Unimplemented: Read as `0' LSPD: Low-Speed Direct Connection Enable bit (U1EP0 only)(1) 1 = Direct connection to a low-speed device enabled 0 = Direct connection to a low-speed device disabled RETRYDIS: Retry Disable bit (U1EP0 only)(1) 1 = Retry NAK transactions disabled 0 = Retry NAK transactions enabled; retry done in hardware Unimplemented: Read as `0' EPCONDIS: Bidirectional Endpoint Control bit If EPTXEN and EPRXEN = 1: 1 = Disable Endpoint n from Control transfers; only Tx and Rx transfers allowed 0 = Enable Endpoint n for Control (SETUP) transfers; Tx and Rx transfers also allowed. For all other combinations of EPTXEN and EPRXEN: This bit is ignored. EPRXEN: Endpoint Receive Enable bit 1 = Endpoint n receive enabled 0 = Endpoint n receive disabled EPTXEN: Endpoint Transmit Enable bit 1 = Endpoint n transmit enabled 0 = Endpoint n transmit disabled EPSTALL: Endpoint Stall Status bit 1 = Endpoint n was stalled 0 = Endpoint n was not stalled EPHSHK: Endpoint Handshake Enable bit 1 = Endpoint handshake enabled 0 = Endpoint handshake disabled (typically used for isochronous endpoints) These bits are available only for U1EP0, and only in Host mode. For all other U1EPn registers, these bits are always unimplemented and read as `0'.
bit 6
bit 5 bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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17.7.4 USB VBUS POWER CONTROL REGISTER REGISTER 17-22: U1PWMCON: USB VBUS PWM GENERATOR CONTROL REGISTER
R/W-0 PWMEN bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 PWMPOL R/W-0 CNTEN bit 8
PWMEN: PWM Enable bit 1 = PWM generator is enabled 0 = PWM generator is disabled; output is held in Reset state specified by PWMPOL Unimplemented: Read as `0' PWMPOL: PWM Polarity bit 1 = PWM output is active-low and resets high 0 = PWM output is active-high and resets low CNTEN: PWM Counter Enable bit 1 = Counter is enabled 0 = Counter is disabled Unimplemented: Read as `0'
bit 14-10 bit 9
bit 8
bit 7-0
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NOTES:
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18.0
Note:
PARALLEL MASTER PORT (PMP)
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 13. Parallel Master Port (PMP)" (DS39713).
Key features of the PMP module include: * Up to 16 Programmable Address Lines * Up to 2 Chip Select Lines * Programmable Strobe Options: - Individual Read and Write Strobes or; - Read/Write Strobe with Enable Strobe * Address Auto-Increment/Auto-Decrement * Programmable Address/Data Multiplexing * Programmable Polarity on Control Signals * Legacy Parallel Slave Port Support * Enhanced Parallel Slave Support: - Address Support - 4-Byte Deep Auto-Incrementing Buffer * Programmable Wait States * Selectable Input Voltage Levels
The Parallel Master Port (PMP) module is a parallel 8-bit I/O module, specifically designed to communicate with a wide variety of parallel devices, such as communication peripherals, LCDs, external memory devices and microcontrollers. Because the interface to parallel peripherals varies significantly, the PMP is highly configurable.
FIGURE 18-1:
PMP MODULE OVERVIEW
Address Bus Data Bus Control Lines PMA<0> PMALL PMA<1> PMALH PMA<13:2> PMA<14> PMCS1 PMA<15> PMCS2 PMBE PMRD PMRD/PMWR PMWR PMENB PMD<7:0> PMA<7:0> PMA<15:8> Up to 16-Bit Address
PIC24F Parallel Master Port
EEPROM
Microcontroller
LCD
FIFO Buffer
8-Bit Data
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REGISTER 18-1:
R/W-0 PMPEN bit 15 R/W-0 CSF1 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 CSF0 R/W-0(1) ALP R/W-0(1) CS2P R/W-0(1) CS1P R/W-0 BEP R/W-0 WRSP
PMCON: PARALLEL PORT CONTROL REGISTER
U-0 -- R/W-0 PSIDL R/W-0(1) ADRMUX1 R/W-0(1) ADRMUX0 R/W-0 PTBEEN R/W-0 PTWREN R/W-0 PTRDEN bit 8 R/W-0 RDSP bit 0
PMPEN: Parallel Master Port Enable bit 1 = PMP enabled 0 = PMP disabled, no off-chip access performed Unimplemented: Read as `0' PSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode ADRMUX1:ADRMUX0: Address/Data Multiplexing Selection bits(1) 11 = Reserved 10 = All 16 bits of address are multiplexed on PMD<7:0> pins 01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 3 bits are multiplexed on PMA<10:8> 00 = Address and data appear on separate pins PTBEEN: Byte Enable Port Enable bit (16-Bit Master mode) 1 = PMBE port enabled 0 = PMBE port disabled PTWREN: Write Enable Strobe Port Enable bit 1 = PMWR/PMENB port enabled 0 = PMWR/PMENB port disabled PTRDEN: Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port enabled 0 = PMRD/PMWR port disabled CSF1:CSF0: Chip Select Function bits 11 = Reserved 10 = PMCS1 functions as chip set 01 = Reserved 00 = Reserved ALP: Address Latch Polarity bit(1) 1 = Active-high (PMALL and PMALH) 0 = Active-low (PMALL and PMALH) CS2P: Chip Select 2 Polarity bit(1) 1 = Active-high (PMCS2/PMCS2) 0 = Active-low (PMCS2/PMCS2) CS1P: Chip Select 1 Polarity bit(1) 1 = Active-high (PMCS1/PMCS1) 0 = Active-low (PMCS1/PMCS1) These bits have no effect when their corresponding pins are used as address lines.
bit 14 bit 13
bit 12-11
bit 10
bit 9
bit 8
bit 7-6
bit 5
bit 4
bit 3
Note 1:
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REGISTER 18-1:
bit 2
PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED)
BEP: Byte Enable Polarity bit 1 = Byte enable active-high (PMBE) 0 = Byte enable active-low (PMBE) WRSP: Write Strobe Polarity bit For Slave modes and Master mode 2 (PMMODE<9:8> = 00,01,10): 1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) For Master mode 1 (PMMODE<9:8> = 11): 1 = Enable strobe active-high (PMENB) 0 = Enable strobe active-low (PMENB) RDSP: Read Strobe Polarity bit For Slave modes and Master mode 2 (PMMODE<9:8> = 00,01,10): 1 = Read strobe active-high (PMRD) 0 = Read strobe active-low (PMRD) For Master mode 1 (PMMODE<9:8> = 11): 1 = Read/write strobe active-high (PMRD/PMWR) 0 = Read/write strobe active-low (PMRD/PMWR) These bits have no effect when their corresponding pins are used as address lines.
bit 1
bit 0
Note 1:
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REGISTER 18-2:
R-0 BUSY bit 15 R/W-0 WAITB1(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 WAITB0(1) R/W-0 WAITM3 R/W-0 WAITM2 R/W-0 WAITM1 R/W-0 WAITM0 R/W-0 WAITE1(1)
PMMODE: PARALLEL PORT MODE REGISTER
R/W-0 IRQM0 R/W-0 INCM1 R/W-0 INCM0 R/W-0 MODE16 R/W-0 MODE1 R/W-0 MODE0 bit 8 R/W-0 WAITE0(1) bit 0
R/W-0 IRQM1
BUSY: Busy bit (Master mode only) 1 = Port is busy (not useful when the processor stall is active) 0 = Port is not busy IRQM1:IRQM0: Interrupt Request Mode bits 11 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode) or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only) 10 = No interrupt generated, processor stall activated 01 = Interrupt generated at the end of the read/write cycle 00 = No interrupt generated INCM1:INCM0: Increment Mode bits 11 = PSP read and write buffers auto-increment (Legacy PSP mode only) 10 = Decrement ADDR<10:0> by 1 every read/write cycle 01 = Increment ADDR<10:0> by 1 every read/write cycle 00 = No increment or decrement of address MODE16: 8/16-Bit Mode bit 1 = 16-bit mode: Data register is 16 bits, a read or write to the Data register invokes two 8-bit transfers 0 = 8-bit mode: Data register is 8 bits, a read or write to the Data register invokes one 8-bit transfer MODE1:MODE0: Parallel Port Mode Select bits 11 = Master mode 1 (PMCS1, PMRD/PMWR, PMENB, PMBE, PMA and PMD<7:0>) 10 = Master mode 2 (PMCS1, PMRD, PMWR, PMBE, PMA and PMD<7:0>) 01 = Enhanced PSP, control signals (PMRD, PMWR, PMCS1, PMD<7:0> and PMA<1:0>) 00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1 and PMD<7:0>) WAITB1:WAITB0: Data Setup to Read/Write Wait State Configuration bits(1) 11 = Data wait of 4 TCY; multiplexed address phase of 4 TCY 10 = Data wait of 3 TCY; multiplexed address phase of 3 TCY 01 = Data wait of 2 TCY; multiplexed address phase of 2 TCY 00 = Data wait of 1 TCY; multiplexed address phase of 1 TCY WAITM3:WAITM0: Read to Byte Enable Strobe Wait State Configuration bits 1111 = Wait of additional 15 TCY ... 0001 = Wait of additional 1 TCY 0000 = No additional wait cycles (operation forced into one TCY)(2) WAITE1:WAITE0: Data Hold After Strobe Wait State Configuration bits(1) 11 = Wait of 4 TCY 10 = Wait of 3 TCY 01 = Wait of 2 TCY 00 = Wait of 1 TCY WAITB and WAITE bits are ignored whenever WAITM3:WAITM0 = 0000. A single-cycle delay is required between consecutive read and/or write operations.
bit 14-13
bit 12-11
bit 10
bit 9-8
bit 7-6
bit 5-2
bit 1-0
Note 1: 2:
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REGISTER 18-3:
R/W-0 CS2 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PMADDR: PARALLEL PORT ADDRESS REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 CS1 ADDR<13:8>
R/W-0
ADDR<7:0>
CS2: Chip Select 2 bit 1 = Chip select 2 is active 0 = Chip select 2 is inactive CS1: Chip Select 1 bit 1 = Chip select 1 is active 0 = Chip select 1 is inactive ADDR13:ADDR0: Parallel Port Destination Address bits
bit 14
bit 13-0
REGISTER 18-4:
R/W-0 PTEN15 bit 15 R/W-0 PTEN7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14
PMAEN: PARALLEL PORT ENABLE REGISTER
R/W-0 PTEN13 R/W-0 PTEN12 R/W-0 PTEN11 R/W-0 PTEN10 R/W-0 PTEN9 R/W-0 PTEN8 bit 8
R/W-0 PTEN14
R/W-0 PTEN6
R/W-0 PTEN5
R/W-0 PTEN4
R/W-0 PTEN3
R/W-0 PTEN2
R/W-0 PTEN1
R/W-0 PTEN0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PTEN15:PTEN14: PMCSx Strobe Enable bit 1 = PMA15 and PMA14 function as either PMA<15:14> or PMCS2 and PMCS1 0 = PMA15 and PMA14 function as port I/O PTEN13:PTEN2: PMP Address Port Enable bits 1 = PMA<13:2> function as PMP address lines 0 = PMA<13:2> function as port I/O PTEN1:PTEN0: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL 0 = PMA1 and PMA0 pads functions as port I/O
bit 13-2
bit 1-0
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REGISTER 18-5:
R-0 IBF bit 15 R-1 OBE bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HS = Hardware Set bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0, HS OBUF U-0 -- U-0 -- R-1 OB3E R-1 OB2E R-1 OB1E R-1 OB0E bit 0
PMSTAT: PARALLEL PORT STATUS REGISTER
U-0 -- U-0 -- R-0 IB3F R-0 IB2F R-0 IB1F R-0 IB0F bit 8
R/W-0, HS IBOV
IBF: Input Buffer Full Status bit 1 = All writable input buffer registers are full 0 = Some or all of the writable input buffer registers are empty IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full input byte register occurred (must be cleared in software) 0 = No overflow occurred Unimplemented: Read as `0' IB3F:IB0F Input Buffer x Status Full bits 1 = Input buffer contains data that has not been read (reading buffer will clear this bit) 0 = Input buffer does not contain any unread data OBE: Output Buffer Empty Status bit 1 = All readable output buffer registers are empty 0 = Some or all of the readable output buffer registers are full OBUF: Output Buffer Underflow Status bits 1 = A read occurred from an empty output byte register (must be cleared in software) 0 = No underflow occurred Unimplemented: Read as `0' OB3E:OB0E Output Buffer x Status Empty bit 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains data that has not been transmitted
bit 14
bit 13-12 bit 11-8
bit 7
bit 6
bit 5-4 bit 3-0
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REGISTER 18-6:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-2 bit 1 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 RTSECSEL
(1)
PADCFG1: PAD CONFIGURATION CONTROL REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 PMPTTL bit 0
Unimplemented: Read as `0' RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC seconds clock is selected for the RTCC pin 0 = RTCC alarm pulse is selected for the RTCC pin PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module inputs (PMDx, PMCS1) use TTL input buffers 0 = PMP module inputs use Schmitt Trigger input buffers To enable the actual RTCC output, the RTCOE (RCFGCAL<10>)) bit must also be set.
bit 0
Note 1:
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FIGURE 18-2:
Master PMD<7:0> PMCS1 PMRD PMWR
LEGACY PARALLEL SLAVE PORT EXAMPLE
PIC24F Slave PMD<7:0> PMCS1 PMRD PMWR Address Bus Data Bus Control Lines
FIGURE 18-3:
Master PMA<1:0>
ADDRESSABLE PARALLEL SLAVE PORT EXAMPLE
PMA<1:0> PMD<7:0> Write Address Decode PMDOUT1L (0) PIC24F Slave
PMD<7:0>
Read Address Decode PMDIN1L (0) PMDIN1H (1) PMDIN2L (2) PMDIN2H (3)
PMCS1 PMRD PMWR Address Bus Data Bus Control Lines
PMCS1 PMRD PMWR
PMDOUT1H (1) PMDOUT2L (2) PMDOUT2H (3)
TABLE 18-1:
00 01 10 11
SLAVE MODE ADDRESS RESOLUTION
Output Register (Buffer) PMDOUT1<7:0> (0) PMDOUT1<15:8> (1) PMDOUT2<7:0> (2) PMDOUT2<15:8> (3) Input Register (Buffer) PMDIN1<7:0> (0) PMDIN1<15:8> (1) PMDIN2<7:0> (2) PMDIN2<15:8> (3)
PMA<1:0>
FIGURE 18-4:
MASTER MODE, DEMULTIPLEXED ADDRESSING (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS)
PIC24F
PMA<13:0>
PMD<7:0>
PMCS1 PMCS2 PMRD PMWR
Address Bus Data Bus Control Lines
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FIGURE 18-5: MASTER MODE, PARTIALLY MULTIPLEXED ADDRESSING (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS)
PIC24F
PMA<13:8> PMD<7:0> PMA<7:0> PMCS1 PMCS2 PMALL PMRD PMWR
Address Bus Multiplexed Data and Address Bus Control Lines
FIGURE 18-6:
MASTER MODE, FULLY MULTIPLEXED ADDRESSING (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS)
PIC24F
PMD<7:0> PMA<13:8> PMCS1 PMCS2 PMALL PMALH PMRD PMWR
Multiplexed Data and Address Bus Control Lines
FIGURE 18-7:
EXAMPLE OF A MULTIPLEXED ADDRESSING APPLICATION
373 A<7:0> D<7:0> A<15:8> A<15:0> D<7:0> CE OE WR Address Bus Data Bus Control Lines
PIC24F PMD<7:0> PMALL
PMALH PMCS1 PMRD PMWR
373
FIGURE 18-8:
EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION
373 A<7:0> D<7:0> A<10:8> A<10:0> D<7:0> CE OE WR Address Bus Data Bus Control Lines
PIC24F PMD<7:0> PMALL PMA<10:8> PMCS1 PMRD PMWR
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FIGURE 18-9:
PIC24F PMD<7:0> PMALL PMCS1 PMRD PMWR
EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION
Parallel Peripheral AD<7:0> ALE CS RD WR Address Bus Data Bus Control Lines
FIGURE 18-10:
PIC24F
PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 8-BIT DATA)
Parallel EEPROM A D<7:0> CE OE WR Address Bus Data Bus Control Lines
PMA PMD<7:0> PMCS1 PMRD PMWR
FIGURE 18-11:
PIC24F
PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 16-BIT DATA)
Parallel EEPROM A D<7:0> A0 CE OE WR Address Bus Data Bus Control Lines
PMA PMD<7:0> PMBE PMCS1 PMRD PMWR
FIGURE 18-12:
PIC24F
LCD CONTROL EXAMPLE (BYTE MODE OPERATION)
LCD Controller D<7:0> RS
PM<7:0> PMA0 PMRD/PMWR PMCS1
R/W
E
Address Bus Data Bus Control Lines
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19.0
Note:
REAL-TIME CLOCK AND CALENDAR (RTCC)
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 29. Real-Time Clock and Calendar (RTCC)" (DS39696).
FIGURE 19-1:
RTCC BLOCK DIAGRAM
RTCC Clock Domain CPU Clock Domain RCFGCAL RTCC Prescalers 0.5s RTCC Timer Alarm Event RTCVAL ALCFGRPT YEAR MTHDY WKDYHR MINSEC ALMTHDY Compare Registers with Masks Repeat Counter ALRMVAL ALWDHR ALMINSEC
32.768 kHz Input from SOSC Oscillator
Comparator
RTCC Interrupt RTCC Interrupt Logic Alarm Pulse RTCC Pin RTCOE
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19.1 RTCC Module Registers
TABLE 19-2:
ALRMPTR <1:0> 00 01 10 11 The RTCC module registers are organized into three categories: * RTCC Control Registers * RTCC Value Registers * Alarm Value Registers
ALRMVAL REGISTER MAPPING
Alarm Value Register Window ALRMVAL<15:8> ALRMVAL<7:0> ALRMMIN ALRMWD ALRMMNTH -- ALRMSEC ALRMHR ALRMDAY --
19.1.1
REGISTER MAPPING
To limit the register interface, the RTCC Timer and Alarm Time registers are accessed through corresponding register pointers. The RTCC Value register window (RTCVALH and RTCVALL) uses the RTCPTR bits (RCFGCAL<9:8>) to select the desired Timer register pair (see Table 19-1). By writing the RTCVALH byte, the RTCC Pointer value, RTCPTR<1:0> bits, decrement by one until they reach `00'. Once they reach `00', the MINUTES and SECONDS value will be accessible through RTCVALH and RTCVALL until the pointer value is manually changed.
Considering that the 16-bit core does not distinguish between 8-bit and 16-bit read operations, the user must be aware that when reading either the ALRMVALH or ALRMVALL bytes will decrement the ALRMPTR<1:0> value. The same applies to the RTCVALH or RTCVALL bytes with the RTCPTR<1:0> being decremented. Note: This only applies to read operations and not write operations.
19.1.2
WRITE LOCK
TABLE 19-1:
RTCPTR <1:0> 00 01 10 11
RTCVAL REGISTER MAPPING
RTCC Value Register Window RTCVAL<15:8> MINUTES WEEKDAY MONTH -- RTCVAL<7:0> SECONDS HOURS DAY YEAR
The Alarm Value register window (ALRMVALH and ALRMVALL) uses the ALRMPTR bits (ALCFGRPT<9:8>) to select the desired Alarm register pair (see Table 19-2). By writing the ALRMVALH byte, the Alarm Pointer value, ALRMPTR<1:0> bits, decrement by one until they reach `00'. Once they reach `00', the ALRMMIN and ALRMSEC value will be accessible through ALRMVALH and ALRMVALL until the pointer value is manually changed.
In order to perform a write to any of the RTCC Timer registers, the RTCWREN bit (RCFGCAL<13>) must be set (refer to Example 19-1). Note: To avoid accidental writes to the timer, it is recommended that the RTCWREN bit (RCFGCAL<13>) is kept clear at any other time. For the RTCWREN bit to be set, there is only 1 instruction cycle time window allowed between the unlock sequence and the setting of RTCWREN; therefore, it is recommended that code follow the procedure in Example 19-1. For applications written in C, the unlock sequence should be implemented using in-line assembly.
EXAMPLE 19-1:
asm asm asm asm asm asm
SETTING THE RTCWREN BIT
volatile("disi #5"); volatile("mov #0x55, w7"); volatile("mov w7, _NVMKEY"); volatile("mov #0xAA, w8"); volatile("mov w8, _NVMKEY"); volatile("bset _RCFGCAL, #13");
//set the RTCWREN bit
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19.1.3 RTCC CONTROL REGISTERS RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1)
U-0 -- R/W-0 RTCWREN R-0 RTCSYNC R-0 HALFSEC
(3)
REGISTER 19-1:
R/W-0 RTCEN bit 15 R/W-0 CAL7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15
(2)
R/W-0 RTCOE
R/W-0 RTCPTR1
R/W-0 RTCPTR0 bit 8
R/W-0 CAL6
R/W-0 CAL5
R/W-0 CAL4
R/W-0 CAL3
R/W-0 CAL2
R/W-0 CAL1
R/W-0 CAL0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RTCEN: RTCC Enable bit(2) 1 = RTCC module is enabled 0 = RTCC module is disabled Unimplemented: Read as `0' RTCWREN: RTCC Value Registers Write Enable bit 1 = RTCVALH and RTCVALL registers can be written to by the user 0 = RTCVALH and RTCVALL registers are locked out from being written to by the user RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple resulting in an invalid data read. If the register is read twice and results in the same data, the data can be assumed to be valid. 0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple HALFSEC: Half-Second Status bit(3) 1 = Second half period of a second 0 = First half period of a second RTCOE: RTCC Output Enable bit 1 = RTCC output enabled 0 = RTCC output disabled RTCPTR1:RTCPTR0: RTCC Value Register Window Pointer bits Points to the corresponding RTCC Value registers when reading RTCVALH and RTCVALL registers; the RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches `00'. RTCVAL<15:8>: 00 = MINUTES 01 = WEEKDAY 10 = MONTH 11 = Reserved RTCVAL<7:0>: 00 = SECONDS 01 = HOURS 10 = DAY 11 = YEAR The RCFGCAL register is only affected by a POR. A write to the RTCEN bit is only allowed when RTCWREN = 1. This bit is read-only. It is cleared to `0' on a write to the lower half of the MINSEC register.
bit 14 bit 13
bit 12
bit 11
bit 10
bit 9-8
Note 1: 2: 3:
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REGISTER 19-1:
bit 7-0
RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) (CONTINUED)
CAL7:CAL0: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute ... 01111111 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment 11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute ... 10000000 = Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute The RCFGCAL register is only affected by a POR. A write to the RTCEN bit is only allowed when RTCWREN = 1. This bit is read-only. It is cleared to `0' on a write to the lower half of the MINSEC register.
Note 1: 2: 3:
REGISTER 19-2:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-2 bit 1
PADCFG1: PAD CONFIGURATION CONTROL REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 RTSECSEL(1) R/W-0 PMPTTL bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC seconds clock is selected for the RTCC pin 0 = RTCC alarm pulse is selected for the RTCC pin PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module inputs (PMDx, PMCS1) use TTL input buffers 0 = PMP module inputs use Schmitt Trigger input buffers To enable the actual RTCC output, the RTCOE (RCFGCAL<10>)) bit must also be set.
bit 0
Note 1:
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REGISTER 19-3:
R/W-0 ALRMEN bit 15 R/W-0 ARPT7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 ARPT6 R/W-0 ARPT5 R/W-0 ARPT4 R/W-0 ARPT3 R/W-0 ARPT2 R/W-0 ARPT1
ALCFGRPT: ALARM CONFIGURATION REGISTER
R/W-0 CHIME R/W-0 AMASK3 R/W-0 AMASK2 R/W-0 AMASK1 R/W-0 AMASK0 R/W-0 ALRMPTR1 R/W-0 ALRMPTR0 bit 8 R/W-0 ARPT0 bit 0
ALRMEN: Alarm Enable bit 1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 00h and CHIME = 0) 0 = Alarm is disabled CHIME: Chime Enable bit 1 = Chime is enabled; ARPT<7:0> bits are allowed to roll over from 00h to FFh 0 = Chime is disabled; ARPT<7:0> bits stop once they reach 00h AMASK3:AMASK0: Alarm Mask Configuration bits 0000 = Every half second 0001 = Every second 0010 = Every 10 seconds 0011 = Every minute 0100 = Every 10 minutes 0101 = Every hour 0110 = Once a day 0111 = Once a week 1000 = Once a month 1001 = Once a year (except when configured for February 29th, once every 4 years) 101x = Reserved - do not use 11xx = Reserved - do not use ALRMPTR1:ALRMPTR0: Alarm Value Register Window Pointer bits Points to the corresponding Alarm Value registers when reading ALRMVALH and ALRMVALL registers; the ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches `00'. ALRMVAL<15:8>: 00 = ALRMMIN 01 = ALRMWD 10 = ALRMMNTH 11 = Unimplemented ALRMVAL<7:0>: 00 = ALRMSEC 01 = ALRMHR 10 = ALRMDAY 11 = Unimplemented ARPT7:ARPT0: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times ... 00000000 = Alarm will not repeat The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to FFh unless CHIME = 1.
bit 14
bit 13-10
bit 9-8
bit 7-0
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19.1.4 RTCVAL REGISTER MAPPINGS YEAR: YEAR VALUE REGISTER(1)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-x YRTEN2 R/W-x YRTEN1 R/W-x YRTEN0 R/W-x YRONE3 R/W-x YRONE2 R/W-x YRONE1 R/W-x YRONE0 bit 0
REGISTER 19-4:
U-0 -- bit 15 R/W-x YRTEN3 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-4 bit 3-0 Note 1:
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' YRTEN3:YRTEN0: Binary Coded Decimal Value of Year's Tens Digit; Contains a value from 0 to 9 YRONE3:YRONE0: Binary Coded Decimal Value of Year's Ones Digit; Contains a value from 0 to 9 A write to the YEAR register is only allowed when RTCWREN = 1.
REGISTER 19-5:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12 bit 11-8 bit 7-6 bit 5-4 bit 3-0 Note 1:
MTHDY: MONTH AND DAY VALUE REGISTER(1)
U-0 -- U-0 -- R-x MTHTEN0 R-x MTHONE3 R-x MTHONE2 R-x MTHONE1 R-x MTHONE0 bit 8 U-0 -- R/W-x DAYTEN1 R/W-x DAYTEN0 R/W-x DAYONE3 R/W-x DAYONE2 R/W-x DAYONE1 R/W-x DAYONE0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' MTHTEN0: Binary Coded Decimal Value of Month's Tens Digit; Contains a value of 0 or 1 MTHONE3:MTHONE0: Binary Coded Decimal Value of Month's Ones Digit; Contains a value from 0 to 9 Unimplemented: Read as `0' DAYTEN1:DAYTEN0: Binary Coded Decimal Value of Day's Tens Digit; Contains a value from 0 to 3 DAYONE3:DAYONE0: Binary Coded Decimal Value of Day's Ones Digit; Contains a value from 0 to 9 A write to this register is only allowed when RTCWREN = 1.
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REGISTER 19-6:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 bit 7-6 bit 5-4 bit 3-0 Note 1: W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-x HRTEN1 R/W-x HRTEN0 R/W-x HRONE3 R/W-x HRONE2 R/W-x HRONE1
WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1)
U-0 -- U-0 -- U-0 -- U-0 -- R/W-x WDAY2 R/W-x WDAY1 R/W-x WDAY0 bit 8 R/W-x HRONE0 bit 0
Unimplemented: Read as `0' WDAY2:WDAY0: Binary Coded Decimal Value of Weekday Digit; Contains a value from 0 to 6 Unimplemented: Read as `0' HRTEN1:HRTEN0: Binary Coded Decimal Value of Hour's Tens Digit; Contains a value from 0 to 2 HRONE3:HRONE0: Binary Coded Decimal Value of Hour's Ones Digit; Contains a value from 0 to 9 A write to this register is only allowed when RTCWREN = 1.
REGISTER 19-7:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 bit 11-8 bit 7 bit 6-4 bit 3-0
MINSEC: MINUTES AND SECONDS VALUE REGISTER
R/W-x R/W-x MINTEN1 R/W-x MINTEN0 R/W-x MINONE3 R/W-x MINONE2 R/W-x MINONE1 R/W-x MINONE0 bit 8 R/W-x R/W-x SECTEN1 R/W-x SECTEN0 R/W-x SECONE3 R/W-x SECONE2 R/W-x SECONE1 R/W-x SECONE0 bit 0
MINTEN2
SECTEN2
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' MINTEN2:MINTEN0: Binary Coded Decimal Value of Minute's Tens Digit; Contains a value from 0 to 5 MINONE3:MINONE0: Binary Coded Decimal Value of Minute's Ones Digit; Contains a value from 0 to 9 Unimplemented: Read as `0' SECTEN2:SECTEN0: Binary Coded Decimal Value of Second's Tens Digit; Contains a value from 0 to 5 SECONE3:SECONE0: Binary Coded Decimal Value of Second's Ones Digit; Contains a value from 0 to 9
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19.1.5 ALRMVAL REGISTER MAPPINGS ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER(1)
U-0 -- U-0 -- R/W-x MTHTEN0 R/W-x MTHONE3 R/W-x MTHONE2 R/W-x MTHONE1 R/W-x MTHONE0 bit 8 U-0 -- R/W-x DAYTEN1 R/W-x DAYTEN0 R/W-x DAYONE3 R/W-x DAYONE2 R/W-x DAYONE1 R/W-x DAYONE0 bit 0
REGISTER 19-8:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12 bit 11-8 bit 7-6 bit 5-4 bit 3-0 Note 1:
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' MTHTEN0: Binary Coded Decimal Value of Month's Tens Digit; Contains a value of 0 or 1 MTHONE3:MTHONE0: Binary Coded Decimal Value of Month's Ones Digit; Contains a value from 0 to 9 Unimplemented: Read as `0' DAYTEN1:DAYTEN0: Binary Coded Decimal Value of Day's Tens Digit; Contains a value from 0 to 3 DAYONE3:DAYONE0: Binary Coded Decimal Value of Day's Ones Digit; Contains a value from 0 to 9 A write to this register is only allowed when RTCWREN = 1.
REGISTER 19-9:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 bit 7-6 bit 5-4 bit 3-0 Note 1:
ALWDHR: ALARM WEEKDAY AND HOURS VALUE REGISTER(1)
U-0 -- U-0 -- U-0 -- U-0 -- R/W-x WDAY2 R/W-x WDAY1 R/W-x WDAY0 bit 8 U-0 -- R/W-x HRTEN1 R/W-x HRTEN0 R/W-x HRONE3 R/W-x HRONE2 R/W-x HRONE1 R/W-x HRONE0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' WDAY2:WDAY0: Binary Coded Decimal Value of Weekday Digit; Contains a value from 0 to 6 Unimplemented: Read as `0' HRTEN1:HRTEN0: Binary Coded Decimal Value of Hour's Tens Digit; Contains a value from 0 to 2 HRONE3:HRONE0: Binary Coded Decimal Value of Hour's Ones Digit; Contains a value from 0 to 9 A write to this register is only allowed when RTCWREN = 1.
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REGISTER 19-10:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 bit 11-8 bit 7 bit 6-4 bit 3-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-x SECTEN2 R/W-x SECTEN1 R/W-x SECTEN0 R/W-x SECONE3 R/W-x SECONE2 R/W-x SECONE1
ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER
R/W-x MINTEN1 R/W-x MINTEN0 R/W-x MINONE3 R/W-x MINONE2 R/W-x MINONE1 R/W-x MINONE0 bit 8 R/W-x SECONE0 bit 0
R/W-x MINTEN2
Unimplemented: Read as `0' MINTEN2:MINTEN0: Binary Coded Decimal Value of Minute's Tens Digit; Contains a value from 0 to 5 MINONE3:MINONE0: Binary Coded Decimal Value of Minute's Ones Digit; Contains a value from 0 to 9 Unimplemented: Read as `0' SECTEN2:SECTEN0: Binary Coded Decimal Value of Second's Tens Digit; Contains a value from 0 to 5 SECONE3:SECONE0: Binary Coded Decimal Value of Second's Ones Digit; Contains a value from 0 to 9
19.2
Calibration
3.
The real-time crystal input can be calibrated using the periodic auto-adjust feature. When properly calibrated, the RTCC can provide an error of less than 3 seconds per month. This is accomplished by finding the number of error clock pulses for one minute and storing the value into the lower half of the RCFGCAL register. The 8-bit signed value loaded into the lower half of RCFGCAL is multiplied by four and will be either added or subtracted from the RTCC timer, once every minute. Refer to the steps below for RTCC calibration: 1. Using another timer resource on the device, the user must find the error of the 32.768 kHz crystal. Once the error is known, it must be converted to the number of error clock pulses per minute and loaded into the RCFGCAL register.
a) If the oscillator is faster then ideal (negative result form step 2), the RCFGCAL register value needs to be negative. This causes the specified number of clock pulses to be subtracted from the timer counter once every minute. b) If the oscillator is slower then ideal (positive result from step 2) the RCFGCAL register value needs to be positive. This causes the specified number of clock pulses to be subtracted from the timer counter once every minute.
4.
Divide the number of error clocks per minute by 4 to get the correct CAL value and load the RCFGCAL register with the correct value. (Each 1-bit increment in CAL adds or subtracts 4 pulses).
2.
EQUATION 19-1:
RTCC CALIBRATION
Writes to the lower half of the RCFGCAL register should only occur when the timer is turned off, or immediately after the rising edge of the seconds pulse. Note: It is up to the user to include in the error value the initial error of the crystal, drift due to temperature and drift due to crystal aging.
Error (clocks per minute) =(Ideal Frequency - Measured Frequency) * 60 Ideal frequency = 32,768 Hz
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19.3 Alarm
* Configurable from half second to one year * Enabled using the ALRMEN bit (ALCFGRPT<15>, Register 19-3) * One-time alarm and repeat alarm options available After each alarm is issued, the value of the ARPT bits is decremented by one. Once the value has reached 00h, the alarm will be issued one last time, after which the ALRMEN bit will be cleared automatically and the alarm will turn off. Indefinite repetition of the alarm can occur if the CHIME bit = 1. Instead of the alarm being disabled when the value of the ARPT bits reaches 00h, it rolls over to FFh and continues counting indefinitely while CHIME is set.
19.3.1
CONFIGURING THE ALARM
The alarm feature is enabled using the ALRMEN bit. This bit is cleared when an alarm is issued. Writes to ALRMVAL should only take place when ALRMEN = 0. As shown in Figure 19-2, the interval selection of the alarm is configured through the AMASK bits (ALCFGRPT<13:10>). These bits determine which and how many digits of the alarm must match the clock value for the alarm to occur. The alarm can also be configured to repeat based on a preconfigured interval. The amount of times this occurs once the alarm is enabled is stored in the ARPT bits, ARPT7:ARPT0 (ALCFGRPT<7:0>). When the value of the ARPT bits equals 00h and the CHIME bit (ALCFGRPT<14>) is cleared, the repeat function is disabled and only a single alarm will occur. The alarm can be repeated up to 255 times by loading ARPT7:ARPT0 with FFh.
19.3.2
ALARM INTERRUPT
At every alarm event, an interrupt is generated. In addition, an alarm pulse output is provided that operates at half the frequency of the alarm. This output is completely synchronous to the RTCC clock and can be used as a trigger clock to other peripherals. Note: Changing any of the registers, other then the RCFGCAL and ALCFGRPT registers and the CHIME bit while the alarm is enabled (ALRMEN = 1), can result in a false alarm event leading to a false alarm interrupt. To avoid a false alarm event, the timer and alarm values should only be changed while the alarm is disabled (ALRMEN = 0). It is recommended that the ALCFGRPT register and CHIME bit be changed when RTCSYNC = 0.
FIGURE 19-2:
ALARM MASK SETTINGS
Day of the Week
Alarm Mask Setting (AMASK3:AMASK0) 0000 - Every half second 0001 - Every second 0010 - Every 10 seconds 0011 - Every minute 0100 - Every 10 minutes 0101 - Every hour 0110 - Every day 0111 - Every week 1000 - Every month 1001 - Every year(1) Note 1:
Month
Day
Hours
Minutes
Seconds
s s m m m s s s s s
h d d m m d d d h h h
h h h h
m m m m
m m m m
s s s s
s s s s
Annually, except when configured for February 29.
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PIC24FJ256GB110 FAMILY
20.0 PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) GENERATOR
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 30. Programmable Cyclic Redundancy Check (CRC)" (DS39714). Consider the CRC equation: x16 + x12 + x5 + 1 To program this polynomial into the CRC generator, the CRC register bits should be set as shown in Table 20-1.
Note:
TABLE 20-1:
Bit Name PLEN3:PLEN0 X15:X1
EXAMPLE CRC SETUP
Bit Value 1111 000100000010000
The programmable CRC generator offers the following features: * User-programmable polynomial CRC equation * Interrupt output * Data FIFO The module implements a software configurable CRC generator. The terms of the polynomial and its length can be programmed using the X15:X1 bits (CRCXOR<15:1>) and the PLEN3:PLEN0 bits (CRCCON<3:0>), respectively.
Note that for the value of X15:X1, the 12th bit and the 5th bit are set to `1', as required by the equation. The 0 bit required by the equation is always XORed. For a 16-bit polynomial, the 16th bit is also always assumed to be XORed; therefore, the X<15:1> bits do not have the 0 bit or the 16th bit. The topology of a standard CRC generator is shown in Figure 20-2.
FIGURE 20-1:
CRC SHIFTER DETAILS
PLEN<3:0>
0
1 CRC Shift Register
2
15
Hold XOR DOUT
X1 0 1
Hold
X2 0 1
Hold
X3 0 1
X15 0 1
Hold
OUT IN BIT 0
OUT IN BIT 1
OUT IN BIT 2
OUT IN BIT 15
p_clk
p_clk
p_clk
p_clk
CRC Read Bus
CRC Write Bus
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Preliminary
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FIGURE 20-2:
XOR D SDOx BIT 0 BIT 4 BIT 5 BIT 12 BIT 15 Q D Q D Q D Q D Q
CRC GENERATOR RECONFIGURED FOR x16 + x12 + x5 + 1
p_clk
p_clk
p_clk
p_clk
p_clk
CRC Read Bus
CRC Write Bus
20.1
20.1.1
User Interface
DATA INTERFACE
To empty words already written into a FIFO, the CRCGO bit must be set to `1' and the CRC shifter allowed to run until the CRCMPT bit is set. Also, to get the correct CRC reading, it will be necessary to wait for the CRCMPT bit to go high before reading the CRCWDAT register. If a word is written when the CRCFUL bit is set, the VWORD Pointer will roll over to 0. The hardware will then behave as if the FIFO is empty. However, the condition to generate an interrupt will not be met; therefore, no interrupt will be generated (See Section 20.1.2 "Interrupt Operation"). At least one instruction cycle must pass after a write to CRCWDAT before a read of the VWORD bits is done.
To start serial shifting, a `1' must be written to the CRCGO bit. The module incorporates a FIFO that is 8 deep when the value of the PLEN bits (CRCCON<3:0>) > 7, and 16 deep, otherwise. The data for which the CRC is to be calculated must first be written into the FIFO. The smallest data element that can be written into the FIFO is one byte. For example, if PLEN = 5, then the size of the data is PLEN + 1 = 6. The data must be written as follows: data[5:0] = crc_input[5:0] data[7:6] = `bxx Once data is written into the CRCWDAT MSb (as defined by PLEN), the value of the VWORD bits (CRCCON<12:8>) increments by one. The serial shifter starts shifting data into the CRC engine when CRCGO = 1 and VWORD > 0. When the MSb is shifted out, VWORD decrements by one. The serial shifter continues shifting until the VWORD reaches 0. Therefore, for a given value of PLEN, it will take (PLEN + 1) * VWORD number of clock cycles to complete the CRC calculations. When VWORD reaches 8 (or 16), the CRCFUL bit will be set. When VWORD reaches 0, the CRCMPT bit will be set. To continually feed data into the CRC engine, the recommended mode of operation is to initially "prime" the FIFO with a sufficient number of words so no interrupt is generated before the next word can be written. Once that is done, start the CRC by setting the CRCGO bit to `1'. From that point onward, the VWORD bits should be polled. If they read less than 8 or 16, another word can be written into the FIFO.
20.1.2
INTERRUPT OPERATION
When the VWORD4:VWORD0 bits make a transition from a value of `1' to `0', an interrupt will be generated.
20.2
20.2.1
Operation in Power Save Modes
SLEEP MODE
If Sleep mode is entered while the module is operating, the module will be suspended in its current state until clock execution resumes.
20.2.2
IDLE MODE
To continue full module operation in Idle mode, the CSIDL bit must be cleared prior to entry into the mode. If CSIDL = 1, the module will behave the same way as it does in Sleep mode; pending interrupt events will be passed on, even though the module clocks are not available.
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20.3 Registers
There are four registers used to control programmable CRC operation: * * * * CRCCON CRCXOR CRCDAT CRCWDAT
REGISTER 20-1:
U-0 -- bit 15 R-0 CRCFUL bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13
CRCCON: CRC CONTROL REGISTER
U-0 -- R/W-0 CSIDL R-0 VWORD4 R-0 VWORD3 R-0 VWORD2 R-0 VWORD1 R-0 VWORD0 bit 8 R-1 U-0 -- R/W-0 CRCGO R/W-0 PLEN3 R/W-0 PLEN2 R/W-0 PLEN1 R/W-0 PLEN0 bit 0
CRCMPT
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' CSIDL: CRC Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode VWORD4:VWORD0: Pointer Value bits Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN3:PLEN0 > 7, or 16 when PLEN3:PLEN0 7. CRCFUL: FIFO Full bit 1 = FIFO is full 0 = FIFO is not full CRCMPT: FIFO Empty Bit 1 = FIFO is empty 0 = FIFO is not empty Unimplemented: Read as `0' CRCGO: Start CRC bit 1 = Start CRC serial shifter 0 = CRC serial shifter turned off PLEN3:PLEN0: Polynomial Length bits Denotes the length of the polynomial to be generated minus 1.
bit 12-8
bit 7
bit 6
bit 5 bit 4
bit 3-0
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REGISTER 20-2:
R/W-0 X15 bit 15 R/W-0 X7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-1 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 X6 R/W-0 X5 R/W-0 X4 R/W-0 X3 R/W-0 X2 R/W-0 X1 U-0 -- bit 0
CRCXOR: CRC XOR POLYNOMIAL REGISTER
R/W-0 X13 R/W-0 X12 R/W-0 X11 R/W-0 X10 R/W-0 X9 R/W-0 X8 bit 8 X14
R/W-0
X15:X1: XOR of Polynomial Term Xn Enable bits Unimplemented: Read as `0'
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21.0
Note:
10-BIT HIGH-SPEED A/D CONVERTER
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 17. 10-Bit A/D Converter" (DS39705).
A block diagram of the A/D Converter is shown in Figure 21-1. To perform an A/D conversion: 1. Configure the A/D module: a) Configure port pins as analog inputs and/or select band gap reference inputs (AD1PCFGL<15:0> and AD1PCFGH<1:0>). b) Select voltage reference source to match expected range on analog inputs (AD1CON2<15:13>). c) Select the analog conversion clock to match desired data rate with processor clock (AD1CON3<7:0>). d) Select the appropriate sample/conversion sequence (AD1CON1<7:5> and AD1CON3<12:8>). e) Select how conversion results are presented in the buffer (AD1CON1<9:8>). f) Select interrupt rate (AD1CON2<5:2>). g) Turn on A/D module (AD1CON1<15>). Configure A/D interrupt (if required): a) Clear the AD1IF bit. b) Select A/D interrupt priority.
The 10-bit A/D Converter has the following key features: * * * * * * * * * * * Successive Approximation (SAR) conversion Conversion speeds of up to 500 ksps 16 analog input pins External voltage reference input pins Internal band gap reference inputs Automatic Channel Scan mode Selectable conversion trigger source 16-word conversion result buffer Selectable Buffer Fill modes Four result alignment options Operation during CPU Sleep and Idle modes
2.
On all PIC24FJ256GB110 family devices, the 10-bit A/D Converter has 16 analog input pins, designated AN0 through AN15. In addition, there are two analog input pins for external voltage reference connections (VREF+ and VREF-). These voltage reference inputs may be shared with other analog input pins.
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Preliminary
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FIGURE 21-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM
Internal Data Bus AVDD AVSS VREF+ VREFVINH AN0 AN1 AN2 AN3 MUX A AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 VBG VBG/2
Sample Control Input MUX Control Pin Config Control VRS/H VR+
VR Select
VR+
16
VRComparator VINL DAC
VINH
10-Bit SAR
Conversion Logic
Data Formatting
VINL
ADC1BUF0: ADC1BUFF AD1CON1 AD1CON2 AD1CON3 AD1CHS0
MUX B
VINH
AD1PCFGL AD1PCFGH AD1CSSL AD1CSSH
VINL
Control Logic
Conversion Control
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REGISTER 21-1:
R/W-0 ADON(1) bit 15 R/W-0 SSRC2 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set HCS = Hardware Clearable/Settable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 SSRC1 R/W-0 SSRC0 U-0 -- U-0 -- R/W-0 ASAM R/W-0, HCS SAMP
AD1CON1: A/D CONTROL REGISTER 1
U-0 -- R/W-0 ADSIDL U-0 -- U-0 -- U-0 -- R/W-0 FORM1 R/W-0 FORM0 bit 8 R/W-0, HCS DONE bit 0
ADON: A/D Operating Mode bit(1) 1 = A/D Converter module is operating 0 = A/D Converter is off Unimplemented: Read as `0' ADSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' FORM1:FORM0: Data Output Format bits 11 = Signed fractional (sddd dddd dd00 0000) 10 = Fractional (dddd dddd dd00 0000) 01 = Signed integer (ssss sssd dddd dddd) 00 = Integer (0000 00dd dddd dddd) SSRC2:SSRC0: Conversion Trigger Source Select bits 111 = Internal counter ends sampling and starts conversion (auto-convert) 110 = Reserved 101 = Reserved 100 = CTMU event ends sampling and starts conversion 011 = Timer5 compare ends sampling and starts conversion 010 = Timer3 compare ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing SAMP bit ends sampling and starts conversion Unimplemented: Read as `0' ASAM: A/D Sample Auto-Start bit 1 = Sampling begins immediately after last conversion completes. SAMP bit is auto-set. 0 = Sampling begins when SAMP bit is set SAMP: A/D Sample Enable bit 1 = A/D sample/hold amplifier is sampling input 0 = A/D sample/hold amplifier is holding DONE: A/D Conversion Status bit 1 = A/D conversion is done 0 = A/D conversion is NOT done Values of ADC1BUFx registers will not retain their values once the ADON bit is cleared. Read out the conversion values from the buffer before disabling the module.
bit 14 bit 13
bit 12-10 bit 9-8
bit 7-5
bit 4-3 bit 2
bit 1
bit 0
Note 1:
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REGISTER 21-2:
R/W-0 VCFG2 bit 15 R-0 BUFS bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' r = Reserved bit' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 SMPI3 R/W-0 SMPI2 R/W-0 SMPI1 R/W-0 SMPI0 R/W-0 BUFM
AD1CON2: A/D CONTROL REGISTER 2
R/W-0 VCFG0 r-0 r U-0 -- R/W-0 CSCNA U-0 -- U-0 -- bit 8 R/W-0 ALTS bit 0
R/W-0 VCFG1
VCFG2:VCFG0: Voltage Reference Configuration bits VCFG2:VCFG0 000 001 010 011 1xx VR+ AVDD External VREF+ pin AVDD External VREF+ pin AVDD VRAVSS AVSS External VREF- pin External VREF- pin AVSS
bit 12 bit 11 bit 10
Reserved: Maintain as `0' Unimplemented: Read as `0' CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Input Multiplexer Setting bit 1 = Scan inputs 0 = Do not scan inputs Unimplemented: Read as `0' BUFS: Buffer Fill Status bit (valid only when BUFM = 1) 1 = A/D is currently filling buffer 08-0F, user should access data in 00-07 0 = A/D is currently filling buffer 00-07, user should access data in 08-0F Unimplemented: Read as `0' SMPI3:SMPI0: Sample/Convert Sequences Per Interrupt Selection bits 1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence 1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence ..... 0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence 0000 = Interrupts at the completion of conversion for each sample/convert sequence BUFM: Buffer Mode Select bit 1 = Buffer configured as two 8-word buffers (ADC1BUFn<15:8> and ADC1BUFn<7:0>) 0 = Buffer configured as one 16-word buffer (ADC1BUFn<15:0>) ALTS: Alternate Input Sample Mode Select bit 1 = Uses MUX A input multiplexer settings for first sample, then alternates between MUX B and MUX A input multiplexer settings for all subsequent samples 0 = Always uses MUX A input multiplexer settings
bit 9-8 bit 7
bit 6 bit 5-2
bit 1
bit 0
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REGISTER 21-3:
R/W-0 ADRC bit 15 R/W-0 ADCS7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set r = Reserved bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 ADCS6 R/W-0 ADCS5 R/W-0 ADCS4 R/W-0 ADCS3 R/W-0 ADCS2 R/W-0 ADCS1 r
AD1CON3: A/D CONTROL REGISTER 3
r-0 r-0 r R/W-0 SAMC4 R/W-0 SAMC3 R/W-0 SAMC2 R/W-0 SAMC1 R/W-0 SAMC0 bit 8 R/W-0 ADCS0 bit 0
ADRC: A/D Conversion Clock Source bit 1 = A/D internal RC clock 0 = Clock derived from system clock Reserved: Maintain as `0' SAMC4:SAMC0: Auto-Sample Time bits 11111 = 31 TAD ***** 00001 = 1 TAD 00000 = 0 TAD (not recommended) ADCS7:ADCS0: A/D Conversion Clock Select bits 11111111 = 256 * TCY ****** 00000001 = 2 * TCY 00000000 = TCY
bit 14-13 bit 12-8
bit 7-0
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REGISTER 21-4:
R/W-0 CH0NB bit 15 R/W-0 CH0NA bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 CH0SA4 R/W-0 CH0SA3 R/W-0 CH0SA2 R/W-0 CH0SA1
AD1CHS0: A/D INPUT SELECT REGISTER
U-0 -- U-0 -- R/W-0 CH0SB4(1) R/W-0 CH0SB3(1) R/W-0 CH0SB2(1) R/W-0 CH0SB1(1) R/W-0 CH0SB0(1) bit 8 R/W-0 CH0SA0 bit 0
CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VRUnimplemented: Read as `0' CH0SB4:CH0SB0: Channel 0 Positive Input Select for MUX B Multiplexer Setting bits(1) 10001 = Channel 0 positive input is internal band gap reference (VBG) 10000 = Channel 0 positive input is VBG/2 01111 = Channel 0 positive input is AN15 01110 = Channel 0 positive input is AN14 01101 = Channel 0 positive input is AN13 01100 = Channel 0 positive input is AN12 01011 = Channel 0 positive input is AN11 01010 = Channel 0 positive input is AN10 01001 = Channel 0 positive input is AN9 01000 = Channel 0 positive input is AN8 00111 = Channel 0 positive input is AN7 00110 = Channel 0 positive input is AN6 00101 = Channel 0 positive input is AN5 00100 = Channel 0 positive input is AN4 00011 = Channel 0 positive input is AN3 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VRUnimplemented: Read as `0' CH0SA4:CH0SA0: Channel 0 Positive Input Select for MUX A Multiplexer Setting bits Implemented combinations are identical to those for CHOSB4:CHOSB0 (above). Combinations not shown here are unimplemented; do not use.
bit 14-13 bit 12-8
bit 7
bit 6-5 bit 4-0
Note 1:
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REGISTER 21-5:
R/W-0 PCFG15 bit 15 R/W-0 PCFG7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 PCFG6 R/W-0 PCFG5 R/W-0 PCFG4 R/W-0 PCFG3 R/W-0 PCFG2 R/W-0 PCFG1
AD1PCFGL: A/D PORT CONFIGURATION REGISTER (LOW)
R/W-0 PCFG13 R/W-0 PCFG12 R/W-0 PCFG11 R/W-0 PCFG10 R/W-0 PCFG9 R/W-0 PCFG8 bit 8 R/W-0 PCFG0 bit 0
R/W-0 PCFG14
PCFG15:PCFG0: Analog Input Pin Configuration Control bits 1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read enabled 0 = Pin configured in Analog mode; I/O port read disabled, A/D samples pin voltage
REGISTER 21-6:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-2 bit 1
AD1PCFGH: A/D PORT CONFIGURATION REGISTER (HIGH)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 PCFG17 R/W-0 PCFG16 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' PCFG17: A/D Input Band Gap Scan Enable bit 1 = Internal band gap (VBG) channel enabled for input scan 0 = Analog channel disabled from input scan PCFG16: A/D Input Half Band Gap Scan Enable bit 1 = Internal VBG/2 channel enabled for input scan 0 = Analog channel disabled from input scan
bit 0
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REGISTER 21-7:
R/W-0 CSSL15 bit 15 R/W-0 CSSL7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 CSSL6 R/W-0 CSSL5 R/W-0 CSSL4 R/W-0 CSSL3 R/W-0 CSSL2 R/W-0 CSSL1
AD1CSSL: A/D INPUT SCAN SELECT REGISTER (LOW)
R/W-0 CSSL13 R/W-0 CSSL12 R/W-0 CSSL11 R/W-0 CSSL10 R/W-0 CSSL9 R/W-0 CSSL8 bit 8 R/W-0 CSSL0 bit 0
R/W-0 CSSL14
CSSL15:CSSL0: A/D Input Pin Scan Selection bits 1 = Corresponding analog channel selected for input scan 0 = Analog channel omitted from input scan
REGISTER 21-8:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-2 bit 1
AD1CSSH: A/D INPUT SCAN SELECT REGISTER (HIGH)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 CSSL17 R/W-0 CSSL16 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' CSSL17: A/D Input Band Gap Scan Selection bit 1 = Internal band gap (VBG) channel selected for input scan 0 = Analog channel omitted from input scan CSSL16: A/D Input Half Band Gap Scan Selection bit 1 = Internal VBG/2 channel selected for input scan 0 = Analog channel omitted from input scan
bit 0
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EQUATION 21-1: A/D CONVERSION CLOCK PERIOD(1)
ADCS = TAD -1 TCY
TAD = TCY * (ADCS + 1)
Note 1:
Based on TCY = 2 * TOSC; Doze mode and PLL are disabled.
FIGURE 21-2:
10-BIT A/D CONVERTER ANALOG INPUT MODEL
VDD ANx VT = 0.6V RIC 250 Sampling Switch RSS CHOLD = DAC capacitance = 4.4 pF (Typical) VSS RSS 5 k (Typical)
Rs VA
CPIN 6-11 pF (Typical)
VT = 0.6V
ILEAKAGE 500 nA
Legend: CPIN = Input Capacitance = Threshold Voltage VT ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Sampling Switch Resistance RSS = Sample/Hold Capacitance (from DAC) CHOLD
Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs 5 k.
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FIGURE 21-3:
Output Code (Binary (Decimal))
A/D TRANSFER FUNCTION
11 1111 1111 (1023) 11 1111 1110 (1022)
10 0000 0011 (515) 10 0000 0010 (514) 10 0000 0001 (513) 10 0000 0000 (512) 01 1111 1111 (511) 01 1111 1110 (510) 01 1111 1101 (509)
00 0000 0001 (1) 00 0000 0000 (0) 1023*(VR+ - VR-) 512*(VR+ - VR-) (VINH - VINL) VR+ - VRVR+ 1024 0 VR-
1024
Voltage Level
VR- +
VR- +
1024
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VR- +
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22.0
Note:
TRIPLE COMPARATOR MODULE
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the associated "PIC24F Family Reference Manual" chapter.
The comparator outputs may be directly connected to the CxOUT pins. When the respective COE equals `1', the I/O pad logic makes the unsynchronized output of the comparator available on the pin. A simplified block diagram of the module in shown in Figure 22-1. Diagrams of the possible individual comparator configurations are shown in Figure 22-2. Each comparator has its own control register, CMxCON (Register 22-1), for enabling and configuring its operation. The output and event status of all three comparators is provided in the CMSTAT register (Register 22-2).
The triple comparator module provides three dual input comparators. The inputs to the comparator can be configured to use any one of four external analog inputs as well, as a voltage reference input from either the internal band gap reference divided by two (VBG/2) or the comparator voltage reference generator.
FIGURE 22-1:
CCH1:CCH0 CREF
TRIPLE COMPARATOR MODULE BLOCK DIAGRAM
EVPOL1:EVPOL0 Trigger/Interrupt Logic CEVT COE
VINCXINB CXINC CXIND VBG/2 VIN+ Input Select Logic C1
CPOL
COUT
C1OUT Pin
EVPOL1:EVPOL0 Trigger/Interrupt Logic CEVT COE
CPOL VINVIN+ C2
COUT
C2OUT Pin
CXINA CVREF VINVIN+ C3
EVPOL1:EVPOL0 Trigger/Interrupt Logic CEVT COE
CPOL
COUT
C3OUT Pin
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FIGURE 22-2: INDIVIDUAL COMPARATOR CONFIGURATIONS
Comparator Off CON = 0, CREF = x, CCH1:CCH0 = xx
VINVIN+ COE
Cx
Off (Read as `0')
CxOUT Pin
Comparator CxINB > CxINA Compare CON = 1, CREF = 0, CCH1:CCH0 = 00
CXINB CXINA VINVIN+ COE
Comparator CxINC > CxINA Compare CON = 1, CREF = 0, CCH1:CCH0 = 01
CXINC CxOUT Pin CXINA VINVIN+ COE
Cx
Cx
CxOUT Pin
Comparator CxIND > CxINA Compare CON = 1, CREF = 0, CCH1:CCH0 = 10
CXIND CXINA VINVIN+ COE
Comparator VBG > CxINA Compare CON = 1, CREF = 0, CCH1:CCH0 = 11 VBG/2
CxOUT Pin CXINA VINVIN+ COE
Cx
Cx
CxOUT Pin
Comparator CxINB > CVREF Compare CON = 1, CREF = 1, CCH1:CCH0 = 00
CXINB CVREF VINVIN+ COE
Comparator CxINC > CVREF Compare CON = 1, CREF = 1, CCH1:CCH0 = 01
CXINC CxOUT Pin CVREF VINVIN+ COE
Cx
Cx
CxOUT Pin
Comparator CxIND > CVREF Compare CON = 1, CREF = 1, CCH1:CCH0 = 10
CXIND CVREF VINVIN+ COE
Comparator VBG > CVREF Compare CON = 1, CREF = 1, CCH1:CCH0 = 11
VBG/2 CxOUT Pin CVREF VINVIN+ COE
Cx
Cx
CxOUT Pin
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REGISTER 22-1:
R/W-0 CON bit 15 R/W-0 EVPOL1 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 EVPOL0 U-0 -- R/W-0 CREF U-0 -- U-0 -- R/W-0 CCH1
CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3)
R/W-0 CPOL U-0 -- U-0 -- U-0 -- R/W-0 CEVT R-0 COUT bit 8 R/W-0 CCH0 bit 0 COE
R/W-0
CON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin. 0 = Comparator output is internal only CPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted Unimplemented: Read as `0' CEVT: Comparator Event bit 1 = Comparator event defined by to EVPOL1:EVPOL0 has occurred; subsequent triggers and interrupts are disabled until the bit is cleared 0 = Comparator event has not occurred COUT: Comparator Output bit When CPOL = 0: 1 = VIN+ > VIN0 = VIN+ < VINWhen CPOL = 1: 1 = VIN+ < VIN0 = VIN+ > VINEVPOL1:EVPOL0: Trigger/Event/Interrupt Polarity Select bits 11 = Trigger/event/interrupt generated on any change of the comparator output (while CEVT = 0) 10 = Trigger/event/interrupt generated on transition of the comparator output: If CPOL = 0 (non-inverted polarity): High-to-low transition only. If CPOL = 1 (inverted polarity): Low-to-high transition only. 01 = Trigger/event/interrupt generated on transition of comparator output: If CPOL = 0 (non-inverted polarity): Low-to-high transition only. If CPOL = 1 (inverted polarity): High-to-low transition only. 00 = Trigger/event/interrupt generation is disabled Unimplemented: Read as `0'
bit 14
bit 13
bit 12-10 bit 9
bit 8
bit 7-6
bit 5
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REGISTER 22-1:
bit 4
CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) (CONTINUED)
CREF: Comparator Reference Select bits (non-inverting input) 1 = Non-inverting input connects to internal CVREF voltage 0 = Non-inverting input connects to CXINA pin Unimplemented: Read as `0' CCH1:CCH0: Comparator Channel Select bits 11 = Inverting input of comparator connects to VBG/2 10 = Inverting input of comparator connects to CXIND pin 01 = Inverting input of comparator connects to CXINC pin 00 = Inverting input of comparator connects to CXINB pin
bit 3-2 bit 1-0
REGISTER 22-2:
R/W-0 CMIDL bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15
CMSTAT: COMPARATOR MODULE STATUS REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- R-0 C3EVT R-0 C2EVT R-0 C1EVT bit 8 U-0 -- U-0 -- U-0 -- U-0 -- R-0 C3OUT R-0 C2OUT R-0 C1OUT bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
CMIDL: Comparator Stop in Idle Mode bit 1 = Discontinue operation of all comparators when device enters Idle mode 0 = Continue operation of all enabled comparators in Idle mode Unimplemented: Read as `0' C3EVT: Comparator 3 Event Status bit (read-only) Shows the current event status of Comparator 3 (CM3CON<9>). C2EVT: Comparator 2 Event Status bit (read-only) Shows the current event status of Comparator 2 (CM2CON<9>). C1EVT: Comparator 1 Event Status bit (read-only) Shows the current event status of Comparator 1 (CM1CON<9>). Unimplemented: Read as `0' C3OUT: Comparator 3 Output Status bit (read-only) Shows the current output of Comparator 3 (CM3CON<8>). C2OUT: Comparator 2 Output Status bit (read-only) Shows the current output of Comparator 2 (CM2CON<8>). C1OUT: Comparator 1 Output Status bit (read-only) Shows the current output of Comparator 1 (CM1CON<8>).
bit 14-11 bit 10 bit 9 bit 8 bit 7-3 bit 2 bit 1 bit 0
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23.0
Note:
COMPARATOR VOLTAGE REFERENCE
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 20. Comparator Voltage Reference Module" (DS39709).
voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON<5>). The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits (CVR3:CVR0), with one range offering finer resolution. The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF-. The voltage source is selected by the CVRSS bit (CVRCON<4>). The settling time of the comparator voltage reference must be considered when changing the CVREF output.
23.1
Configuring the Comparator Voltage Reference
The voltage reference module is controlled through the CVRCON register (Register 23-1). The comparator voltage reference provides two ranges of output
FIGURE 23-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
VREF+ AVDD CVRSS = 1
CVRSS = 0
8R R R R
CVR3:CVR0
CVREN
16 Steps
16-to-1 MUX
R
CVREF
R R R CVRR VREFCVRSS = 1
8R
CVRSS = 0 AVSS
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REGISTER 23-1:
U-0 -- bit 15 R/W-0 CVREN bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 CVROE R/W-0 CVRR R/W-0 CVRSS R/W-0 CVR3 R/W-0 CVR2 R/W-0 CVR1
CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 CVR0 bit 0
Unimplemented: Read as `0' CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on CVREF pin 0 = CVREF voltage level is disconnected from CVREF pin CVRR: Comparator VREF Range Selection bit 1 = CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step size 0 = CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step size CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source CVRSRC = VREF+ - VREF0 = Comparator reference source CVRSRC = AVDD - AVSS CVR3:CVR0: Comparator VREF Value Selection 0 CVR3:CVR0 15 bits When CVRR = 1: CVREF = (CVR<3:0>/ 24) * (CVRSRC) When CVRR = 0: CVREF = 1/4 * (CVRSRC) + (CVR<3:0>/32) * (CVRSRC)
bit 6
bit 5
bit 4
bit 3-0
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24.0
Note:
CHARGE TIME MEASUREMENT UNIT (CTMU)
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the associated "PIC24F Family Reference Manual" chapter.
24.1
Measuring Capacitance
The Charge Time Measurement Unit is a flexible analog module that provides accurate differential time measurement between pulse sources, as well as asynchronous pulse generation. Its key features include: * * * * * * Four edge input trigger sources Polarity control for each edge source Control of edge sequence Control of response to edges Time measurement resolution of 1 nanosecond Accurate current source suitable for capacitive measurement
The CTMU module measures capacitance by generating an output pulse with a width equal to the time between edge events on two separate input channels. The pulse edge events to both input channels can be selected from four sources: two internal peripheral modules (OC1 and Timer1) and two external pins (CTEDG1 and CTEDG2). This pulse is used with the module's precision current source to calculate capacitance according to the relationship: dV C = I -----dT For capacitance measurements, the A/D Converter samples an external capacitor (CAPP) on one of its input channels after the CTMU output's pulse. A precision resistor (RPR) provides current source calibration on a second A/D channel. After the pulse ends, the converter determines the voltage on the capacitor. The actual calculation of capacitance is performed in software by the application. Figure 24-1 shows the external connections used for capacitance measurements, and how the CTMU and A/D modules are related in this application. This example also shows the edge events coming from Timer1, but other configurations using external edge sources are possible. A detailed discussion on measuring capacitance and time with the CTMU module is provided in the "PIC24F Family Reference Manual".
Together with other on-chip analog modules, the CTMU can be used to precisely measure time, measure capacitance, measure relative changes in capacitance, or generate output pulses that are independent of the system clock. The CTMU module is ideal for interfacing with capacitive-based sensors. The CTMU is controlled through two registers, CTMUCON and CTMUICON. CTMUCON enables the module, and controls edge source selection, edge source polarity selection, and edge sequencing. The CTMUICON register has controls the selection and trim of the current source.
FIGURE 24-1:
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT
PIC24F Device Timer1 CTMU EDG1 EDG2 Output Pulse A/D Converter ANx ANY Current Source
CAPP
RPR
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24.2 Measuring Time
Time measurements on the pulse width can be similarly performed, using the A/D module's internal capacitor (CAD) and a precision resistor for current calibration. Figure 24-2 shows the external connections used for time measurements, and how the CTMU and A/D modules are related in this application. This example also shows both edge events coming from the external CTEDG pins, but other configurations using internal edge sources are possible. A detailed discussion on measuring capacitance and time with the CTMU module is provided in the PIC24F Family Reference Manual. When the module is configured for pulse generation delay by setting the TGEN bit (CTMUCON<12>), the internal current source is connected to the B input of Comparator 2. A capacitor (CDELAY) is connected to the Comparator 2 pin, C2INB, and the comparator voltage reference, CVREF, is connected to C2INA. CVREF is then configured for a specific trip point. The module begins to charge CDELAY when an edge event is detected. When CDELAY charges above the CVREF trip point, a pulse is output on CTPLS. The length of the pulse delay is determined by the value of CDELAY and the CVREF trip point. Figure 24-3 shows the external connections for pulse generation, as well as the relationship of the different analog modules required. While CTEDG1 is shown as the input pulse source, other options are available. A detailed discussion on pulse generation with the CTMU module is provided in the "PIC24F Family Reference Manual".
24.3
Pulse Generation and Delay
The CTMU module can also generate an output pulse with edges that are not synchronous with the device's system clock. More specifically, it can generate a pulse with a programmable delay from an edge event input to the module.
FIGURE 24-2:
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT TIME
PIC24F Device CTMU CTEDG1 CTEDG2 EDG1 EDG2 Output Pulse A/D Converter CAD RPR Current Source
ANx
FIGURE 24-3:
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION
PIC24F Device CTEDG1 EDG1 CTMU CTPLS
Current Source Comparator C2INB C2
CDELAY
CVREF
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REGISTER 24-1:
R/W-0 CTMUEN bit 15 R/W-0 EDG2POL bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 EDG2SEL1 R/W-0 EDG2SEL0 R/W-0 EDG1POL R/W-0 EDG1SEL1 R/W-0 EDG1SEL0 R/W-0 EDG2STAT
CTMUCON: CTMU CONTROL REGISTER
U-0 -- R/W-0 CTMUSIDL R/W-0 TGEN R/W-0 EDGEN R/W-0 EDGSEQEN R/W-0 IDISSEN R/W-0 CTTRIG bit 8 R/W-0 EDG1STAT bit 0
CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled Unimplemented: Read as `0' CTMUSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode TGEN: Time Generation Enable bit 1 = Enables edge delay generation 0 = Disables edge delay generation EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked EDGSEQEN: Edge Sequence Enable bit 1 = Edge 1 event must occur before Edge 2 event can occur 0 = No edge sequence is needed IDISSEN: Analog Current Source Control bit 1 = Analog current source output is grounded 0 = Analog current source output is not grounded CTTRIG: Trigger Control bit 1 = Trigger output is enabled 0 = Trigger output is disabled EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 programmed for a positive edge response 0 = Edge 2 programmed for a negative edge response EDG2SEL1:EDG2SEL0: Edge 2 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 programmed for a positive edge response 0 = Edge 1 programmed for a negative edge response
bit 14 bit 13
bit 12
bit 10
bit 10
bit 9
bit 8
bit 7
bit 6-5
bit 4
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REGISTER 24-1:
bit 3-2
CTMUCON: CTMU CONTROL REGISTER (CONTINUED)
EDG1SEL1:EDG1SEL0: Edge 1 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module EDG2STAT: Edge 2 Status bit 1 = Edge 2 event has occurred 0 = Edge 2 event has not occurred EDG1STAT: Edge 1 Status bit 1 = Edge 1 event has occurred 0 = Edge 1 event has not occurred
bit 1
bit 0
REGISTER 24-2:
R/W-0 ITRIM5 bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10
CTMUICON: CTMU CURRENT CONTROL REGISTER
R/W-0 ITRIM3 R/W-0 ITRIM2 R/W-0 ITRIM1 R/W-0 ITRIM0 R/W-0 IRNG1 R/W-0 IRNG0 bit 8 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
R/W-0 ITRIM4
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ITRIM5:ITRIM0: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 ..... 000001 = Minimum positive change from nominal current 000000 = Nominal current output specified by IRNG1:IRNG0 111111 = Minimum negative change from nominal current ..... 100010 100001 = Maximum negative change from nominal current IRNG1:IRNG0: Current Source Range Select bits 11 = 100 x Base current 10 = 10 x Base current 01 = Base current level (0.55 A nominal) 00 = Current source disabled Unimplemented: Read as `0'
bit 9-8
bit 7-0
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25.0
Note:
SPECIAL FEATURES
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the following sections of the "PIC24F Family Reference Manual": * Section 9. "Watchdog Timer (WDT)" (DS39697) * Section 32. "High-Level Device Integration" (DS39719) * Section 33. "Programming and Diagnostics" (DS39716)
25.1.1
CONSIDERATIONS FOR CONFIGURING PIC24FJ256GB110 FAMILY DEVICES
PIC24FJ256GB110 family devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are: * * * * * * Flexible Configuration Watchdog Timer (WDT) Code Protection JTAG Boundary Scan Interface In-Circuit Serial Programming In-Circuit Emulation
In PIC24FJ256GB110 family devices, the configuration bytes are implemented as volatile memory. This means that configuration data must be programmed each time the device is powered up. Configuration data is stored in the three words at the top of the on-chip program memory space, known as the Flash Configuration Words. Their specific locations are shown in Table 25-1. These are packed representations of the actual device Configuration bits, whose actual locations are distributed among several locations in configuration space. The configuration data is automatically loaded from the Flash Configuration Words to the proper Configuration registers during device Resets. Note: Configuration data is reloaded on all types of device Resets.
When creating applications for these devices, users should always specifically allocate the location of the Flash Configuration Word for configuration data. This is to make certain that program code is not stored in this address when the code is compiled. The upper byte of all Flash Configuration Words in program memory should always be `1111 1111'. This makes them appear to be NOP instructions in the remote event that their locations are ever executed by accident. Since Configuration bits are not implemented in the corresponding locations, writing `1's to these locations has no effect on device operation. Note: Performing a page erase operation on the last page of program memory clears the Flash Configuration Words, enabling code protection as a result. Therefore, users should avoid performing page erase operations on the last page of program memory.
25.1
Configuration Bits
The Configuration bits can be programmed (read as `0'), or left unprogrammed (read as `1'), to select various device configurations. These bits are mapped starting at program memory location F80000h. A detailed explanation of the various bit functions is provided in Register 25-1 through Register 25-5. Note that address F80000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (800000h-FFFFFFh) which can only be accessed using table reads and table writes.
TABLE 25-1:
FLASH CONFIGURATION WORD LOCATIONS FOR PIC24FJ256GB110 FAMILY DEVICES
Configuration Word Addresses 1 ABFEh 157FEh 20BFEh 2ABFEh 2 ABFCh 157FC 20BFC 2ABFC 3 ABFAh 157FA 20BFA 2ABFA
Device PIC24FJ64GB1 PIC24FJ128GB1 PIC24FJ192GB1 PIC24FJ256GB1
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REGISTER 25-1:
U-1 -- bit 23 r-x r bit 15 R/PO-1 FWDTEN bit 7 Legend: R = Readable bit PO = Program Once bit -n = Value when device is unprogrammed bit 23-16 bit 15 bit 14 Unimplemented: Read as `1' Reserved: The value is unknown; program as `0' JTAGEN: JTAG Port Enable bit(1) 1 = JTAG port is enabled 0 = JTAG port is disabled GCP: General Segment Program Memory Code Protection bit 1 = Code protection is disabled 0 = Code protection is enabled for the entire program memory space GWRP: General Segment Code Flash Write Protection bit 1 = Writes to program memory are allowed 0 = Writes to program memory are disabled DEBUG: Background Debugger Enable bit 1 = Device resets into Operational mode 0 = Device resets into Debug mode Reserved: Always maintain as `1' ICS1:ICS0: Emulator Pin Placement Select bits 11 = Emulator functions are shared with PGEC1/PGED1 10 = Emulator functions are shared with PGEC2/PGED2 01 = Emulator functions are shared with PGEC3/PGED3 00 = Reserved; do not use FWDTEN: Watchdog Timer Enable bit 1 = Watchdog Timer is enabled 0 = Watchdog Timer is disabled WINDIS: Windowed Watchdog Timer Disable bit 1 = Standard Watchdog Timer enabled 0 = Windowed Watchdog Timer enabled; FWDTEN must be `1' Unimplemented: Read as `1' FWPSA: WDT Prescaler Ratio Select bit 1 = Prescaler ratio of 1:128 0 = Prescaler ratio of 1:32 The JTAGEN bit can only be modified using In-Circuit Serial ProgrammingTM (ICSPTM). It cannot be modified while programming the device through the JTAG interface. r = Reserved bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared R/PO-1 WINDIS U-1 -- R/PO-1 FWPSA R/PO-1 WDTPS3 R/PO-1 WDTPS2 R/PO-1 WDTPS1 R/PO-1 JTAGEN R/PO-1 GCP R/PO-1 GWRP R/PO-1 DEBUG r-1 r R/PO-1 ICS1
CW1: FLASH CONFIGURATION WORD 1
U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- bit 16 R/PO-1 ICS0 bit 8 R/PO-1 WDTPS0 bit 0
bit 13
bit 12
bit 11
bit 10 bit 9-8
bit 7
bit 6
bit 5 bit 4
Note 1:
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REGISTER 25-1:
bit 3-0
CW1: FLASH CONFIGURATION WORD 1 (CONTINUED)
WDTPS3:WDTPS0: Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 The JTAGEN bit can only be modified using In-Circuit Serial ProgrammingTM (ICSPTM). It cannot be modified while programming the device through the JTAG interface.
Note 1:
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REGISTER 25-2:
U-1 -- bit 23 R/PO-1 IESO bit 15 R/PO-1 FCKSM1 bit 7
CW2: FLASH CONFIGURATION WORD 2
U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- bit 16 R/PO-1 FNOSC0 bit 8 R/PO-1 POSCMD0 bit 0
R/PO-1 PLLDIV2
R/PO-1 PLLDIV1
R/PO-1 PLLDIV0
r-0 r
R/PO-1 FNOSC2
R/PO-1 FNOSC1
R/PO-1 FCKSM0
R/PO-1 OSCIOFCN
R/PO-1 IOL1WAY
R/PO-1 DISUVREG
r-1 r
R/PO-1 POSCMD1
Legend: R = Readable bit PO = Program-once bit -n = Value when device is unprogrammed bit 23-16 bit 15
r = Reserved bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared
bit 14-12
bit 11 bit 10-8
bit 7-6
bit 5
bit 4
Unimplemented: Read as `1' IESO: Internal External Switchover bit 1 = IESO mode (Two-Speed Start-up) enabled 0 = IESO mode (Two-Speed Start-up) disabled PLLDIV2:PLLDIV0: USB 96 MHz PLL Prescaler Select bits 111 = Oscillator input divided by 12 (48 MHz input) 110 = Oscillator input divided by 10 (40 MHz input) 101 = Oscillator input divided by 6 (24 MHz input) 100 = Oscillator input divided by 5 (20 MHz input) 011 = Oscillator input divided by 4 (16 MHz input) 010 = Oscillator input divided by 3 (12 MHz input) 001 = Oscillator input divided by 2 (8 MHz input) 000 = Oscillator input used directly (4 MHz input) Reserved: Always maintain as `0' FNOSC2:FNOSC0: Initial Oscillator Select bits 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) FCKSM1:FCKSM0: Clock Switching and Fail-Safe Clock Monitor Configuration bits 1x = Clock switching and Fail-Safe Clock Monitor are disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled OSCIOFCN: OSCO Pin Configuration bit If POSCMD1:POSCMD0 = 11 or 00: 1 = OSCO/CLKO/RC15 functions as CLKO (FOSC/2) 0 = OSCO/CLKO/RC15 functions as port I/O (RC15) If POSCMD1:POSCMD0 = 10 or 01: OSCIOFCN has no effect on OSCO/CLKO/RC15. IOL1WAY: IOLOCK One-Way Set Enable bit 1 = The IOLOCK bit (OSCCON<6>)can be set once, provided the unlock sequence has been completed. Once set, the Peripheral Pin Select registers cannot be written to a second time. 0 = The IOLOCK bit can be set and cleared as needed, provided the unlock sequence has been completed
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REGISTER 25-2:
bit 3
CW2: FLASH CONFIGURATION WORD 2 (CONTINUED)
bit 2 bit 1-0
DISUVREG: Internal USB 3.3V Regulator Disable bit 1 = Regulator is disabled 0 = Regulator is enabled Reserved: Always maintain as `1' POSCMD1:POSCMD0: Primary Oscillator Configuration bits 11 = Primary oscillator disabled 10 = HS Oscillator mode selected 01 = XT Oscillator mode selected 00 = EC Oscillator mode selected
REGISTER 25-3:
U-1 -- bit 23 R/PO-1 WPEND bit 15 R/PO-1 WPFP7 bit 7
CW3: FLASH CONFIGURATION WORD 3
U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- bit 16 R/PO-1 WPFP8 bit 8 R/PO-1 WPFP0 bit 0
R/PO-1 WPCFG
R/PO-1 WPDIS
U-1 --
U-1 --
U-1 --
U-1 --
R/PO-1 WPFP6
R/PO-1 WPFP5
R/PO-1 WPFP4
R/PO-1 WPFP3
R/PO-1 WPFP2
R/PO-1 WPFP1
Legend: R = Readable bit PO = Program-once bit -n = Value when device is unprogrammed bit 23-16 bit 15
U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared
bit 14
bit 13
bit 12-9 bit 8-0
Unimplemented: Read as `1' WPEND: Segment Write Protection End Page Select bit 1 = Protected code segment lower boundary is at the bottom of program memory (000000h); upper boundary is the code page specified by WPFP8:WPFP0 0 = Protected code segment upper boundary is at the last page of program memory; lower boundary is the code page specified by WPFP8:WPFP0 WPCFG: Configuration Word Code Page Protection Select bit 1 = Last page (at the top of program memory) and Flash Configuration Words are not protected 0 = Last page and Flash Configuration Words are code protected WPDIS: Segment Write Protection Disable bit 1 = Segmented code protection disabled 0 = Segmented code protection enabled; protected segment defined by WPEND, WPCFG and WPFPx Configuration bits Unimplemented: Read as `1' WPFP8:WPFP0: Protected Code Segment Boundary Page bits Designates the 16 K word program code page that is the boundary of the protected code segment, starting with Page 0 at the bottom of program memory. If WPEND = 1: Last address of designated code page is the upper boundary of the segment. If WPEND = `0': First address of designated code page is the lower boundary of the segment.
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REGISTER 25-4:
U -- bit 23 U -- bit 15 R FAMID1 bit 7
DEVID: DEVICE ID REGISTER
U -- U -- U -- U -- U -- U -- U -- bit 16 R FAMID2 bit 8 R DEV0 bit 0
U --
R FAMID7
R FAMID6
R FAMID5
R FAMID4
R FAMID3
R FAMID0
R DEV5
R DEV4
R DEV3
R DEV2
R DEV1
Legend: R = Read-only bit bit 23-14 bit 13-6 bit 5-0
U = Unimplemented bit
Unimplemented: Read as `1' FAMID7:FAMID0: Device Family Identifier bits 01000000 = PIC24FJ256GB110 family DEV5:DEV0: Individual Device Identifier bits 000001 = PIC24FJ64GB106 000011 = PIC24FJ64GB108 000111 = PIC24FJ64GB110 001001 = PIC24FJ128GB106 001011 = PIC24FJ128GB108 001111 = PIC24FJ128GB110 010001 = PIC24FJ192GB106 010011 = PIC24FJ192GB108 010111 = PIC24FJ192GB110 011001 = PIC24FJ256GB106 011011 = PIC24FJ256GB108 011111 = PIC24FJ256GB110
REGISTER 25-5:
U -- bit 23 U -- bit 15 R MAJRV1 bit 7
DEVREV: DEVICE REVISION REGISTER
U -- U -- U -- U -- U -- U -- U -- bit 16 R MAJRV2 bit 8 R DOT0 bit 0
U --
U --
U --
U --
U --
U --
R MAJRV0
U --
U --
U --
R DOT2
R DOT1
Legend: R = Read-only bit bit 23-9 bit 8-6 bit 5-3 bit 2-0
U = Unimplemented bit
Unimplemented: Read as `0' MAJRV2:MAJRV0: Major Revision Identifier bits Unimplemented: Read as `0' DOT2:DOT0: Minor Revision Identifier bits
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25.2 On-Chip Voltage Regulator
FIGURE 25-1:
All PIC24FJ256GB110 family devices power their core digital logic at a nominal 2.5V. This may create an issue for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the PIC24FJ256GB110 family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator is controlled by the ENVREG pin. Tying VDD to the pin enables the regulator, which in turn, provides power to the core from the other VDD pins. When the regulator is enabled, a low ESR capacitor (such as ceramic) must be connected to the VDDCORE/VCAP pin (Figure 25-1). This helps to maintain the stability of the regulator. The recommended value for the filter capacitor (CEFC) is provided in Section 28.1 "DC Characteristics". If ENVREG is tied to VSS, the regulator is disabled. In this case, separate power for the core logic at a nominal 2.5V must be supplied to the device on the VDDCORE/VCAP pin to run the I/O pins at higher voltage levels, typically 3.3V. Alternatively, the VDDCORE/VCAP and VDD pins can be tied together to operate at a lower nominal voltage. Refer to Figure 25-1 for possible configurations.
CONNECTIONS FOR THE ON-CHIP REGULATOR
Regulator Enabled (ENVREG tied to VDD): 3.3V PIC24FJ256GB VDD ENVREG VDDCORE/VCAP CEFC (10 F typ) VSS
Regulator Disabled (ENVREG tied to ground): 2.5V(1) 3.3V(1) PIC24FJ256GB VDD ENVREG VDDCORE/VCAP VSS
25.2.1
VOLTAGE REGULATOR TRACKING MODE AND LOW-VOLTAGE DETECTION
Regulator Disabled (VDD tied to VDDCORE): 2.5V(1) PIC24FJ256GB VDD ENVREG VDDCORE/VCAP VSS
When it is enabled, the on-chip regulator provides a constant voltage of 2.5V nominal to the digital core logic. The regulator can provide this level from a VDD of about 2.5V, all the way up to the device's VDDMAX. It does not have the capability to boost VDD levels below 2.5V. In order to prevent "brown out" conditions when the voltage drops too low for the regulator, the regulator enters Tracking mode. In Tracking mode, the regulator output follows VDD, with a typical voltage drop of 100 mV. When the device enters Tracking mode, it is no longer possible to operate at full speed. To provide information about when the device enters Tracking mode, the on-chip regulator includes a simple, Low-Voltage Detect circuit. When VDD drops below full-speed operating voltage, the circuit sets the Low-Voltage Detect Interrupt Flag, LVDIF (IFS4<8>). This can be used to generate an interrupt and put the application into a low-power operational mode, or trigger an orderly shutdown. Low-Voltage Detection is only available when the regulator is enabled.
Note 1:
These are typical operating voltages. Refer to Section 28.1 "DC Characteristics" for the full operating ranges of VDD and VDDCORE.
25.2.2
ON-CHIP REGULATOR AND POR
When the voltage regulator is enabled, it takes approximately 500 s for it to generate output. During this time, designated as TSTARTUP, code execution is disabled. TSTARTUP is applied every time the device resumes operation after any power-down, including Sleep mode. If the regulator is disabled, a separate Power-up Timer (PWRT) is automatically enabled. The PWRT adds a fixed delay of 64 ms nominal delay at device start-up.
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25.2.3 ON-CHIP REGULATOR AND BOR
25.3
Watchdog Timer (WDT)
When the on-chip regulator is enabled, PIC24FJ256GB110 family devices also have a simple brown-out capability. If the voltage supplied to the regulator is inadequate to maintain the tracking level, the regulator Reset circuitry will generate a Brown-out Reset. This event is captured by the BOR flag bit (RCON<1>). The brown-out voltage specifications are provided in Section 7. Reset" (DS39712) in the "PIC24F Family Reference Manual".
For PIC24FJ256GB110 family devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 31 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the FWPSA Configuration bit. With a 31 kHz input, the prescaler yields a nominal WDT time-out period (TWDT) of 1 ms in 5-bit mode, or 4 ms in 7-bit mode. A variable postscaler divides down the WDT prescaler output and allows for a wide range of time-out periods. The postscaler is controlled by the WDTPS3:WDTPS0 Configuration bits (CW1<3:0>), which allow the selection of a total of 16 settings, from 1:1 to 1:32,768. Using the prescaler and postscaler, time-out periods ranging from 1 ms to 131 seconds can be achieved. The WDT, prescaler and postscaler are reset: * On any device Reset * On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit after changing the NOSC bits), or by hardware (i.e., Fail-Safe Clock Monitor) * When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered) * When the device exits Sleep or Idle mode to resume normal operation * By a CLRWDT instruction during normal execution If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device will wake the device and code execution will continue from where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE bits (RCON<3:2>) will need to be cleared in software after the device wakes up. The WDT Flag bit, WDTO (RCON<4>), is not automatically cleared following a WDT time-out. To detect subsequent WDT events, the flag must be cleared in software. Note: The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed.
25.2.4
POWER-UP REQUIREMENTS
The on-chip regulator is designed to meet the power-up requirements for the device. If the application does not use the regulator, then strict power-up conditions must be adhered to. While powering up, VDDCORE must never exceed VDD by 0.3 volts. Note: For more information, see Section 28.0 "Electrical Characteristics".
25.2.5
VOLTAGE REGULATOR STANDBY MODE
When enabled, the on-chip regulator always consumes a small incremental amount of current over IDD/IPD, including when the device is in Sleep mode, even though the core digital logic does not require power. To provide additional savings in applications where power resources are critical, the regulator automatically disables itself whenever the device goes into Sleep mode. This feature is controlled by the VREGS bit (RCON<8>). By default, this bit is cleared, which enables Standby mode. When waking up from Standby mode, the regulator will require around 190 s to wake-up. This extra time is needed to ensure that the regulator can source enough current to power the Flash memory. For applications which require a faster wake-up time, it is possible to disable regulator Standby mode. The VREGS bit (RCON<8>) can be set to turn off Standby mode so that the Flash stays powered when in Sleep mode and the device can wake-up in 10 s. When VREGS is set, the power consumption while in Sleep mode, will be approximately 40 A higher than power consumption when the regulator is allowed to enter Standby mode.
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25.3.1 WINDOWED OPERATION 25.3.2 CONTROL REGISTER
The Watchdog Timer has an optional fixed-window mode of operation. In this Windowed mode, CLRWDT instructions can only reset the WDT during the last 1/4 of the programmed WDT period. A CLRWDT instruction executed before that window causes a WDT Reset, similar to a WDT time-out. Windowed WDT mode is enabled by programming the WINDIS Configuration bit (CW1<6>) to `0'. The WDT is enabled or disabled by the FWDTEN Configuration bit. When the FWDTEN Configuration bit is set, the WDT is always enabled. The WDT can be optionally controlled in software when the FWDTEN Configuration bit has been programmed to `0'. The WDT is enabled in software by setting the SWDTEN control bit (RCON<5>). The SWDTEN control bit is cleared on any device Reset. The software WDT option allows the user to enable the WDT for critical code segments and disable the WDT during non-critical segments for maximum power savings.
FIGURE 25-2:
SWDTEN FWDTEN
WDT BLOCK DIAGRAM
LPRC Control FWPSA Prescaler (5-bit/7-bit) 31 kHz 1 ms/4 ms WDT Counter WDTPS3:WDTPS0 Postscaler 1:1 to 1:32.768 WDT Overflow Reset Wake from Sleep
LPRC Input
All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode CLRWDT Instr. PWRSAV Instr. Sleep or Idle Mode
25.4
Program Verification and Code Protection
25.4.2
CODE SEGMENT PROTECTION
PIC24FJ256GB110 family devices provide two complimentary methods to protect application code from overwrites and erasures. These also help to protect the device from inadvertent configuration changes during run time.
25.4.1
GENERAL SEGMENT PROTECTION
For all devices in the PIC24FJ256GB110 family, the on-chip program memory space is treated as a single block, known as the General Segment (GS). Code protection for this block is controlled by one Configuration bit, GCP. This bit inhibits external reads and writes to the program memory space. It has no direct effect in normal execution mode. Write protection is controlled by the GWRP bit in the Configuration Word. When GWRP is programmed to `0', internal write and erase operations to program memory are blocked.
In addition to global General Segment protection, a separate subrange of the program memory space can be individually protected against writes and erases. This area can be used for many purposes where a separate block of write and erase protected code is needed, such as bootloader applications. Unlike common boot block implementations, the specially protected segment in PIC24FJ256GB110 family devices can be located by the user anywhere in the program space, and configured in a wide range of sizes. Code segment protection provides an added level of protection to a designated area of program memory, by disabling the NVM safety interlock whenever a write or erase address falls within a specified range. They do not override General Segment protection controlled by the GCP or GWRP bits. For example, if GCP and GWRP are enabled, enabling segmented code protection for the bottom half of program memory does not undo General Segment protection for the top half.
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The size and type of protection for the segmented code range are configured by the WPFPx, WPEND, WPCFG and WPDIS bits in Configuration Word 3. Code segment protection is enabled by programming the WPDIS bit (= 0). The WPFP bits specify the size of the segment to be protected, by specifying the 512-word code page that is the start or end of the protected segment. The specified region is inclusive, therefore, this page will also be protected. The WPEND bit determines if the protected segment uses the top or bottom of the program space as a boundary. Programming WPEND (= 0) sets the bottom of program memory (000000h) as the lower boundary of the protected segment. Leaving WPEND unprogrammed (= 1) protects the specified page through the last page of implemented program memory, including the Configuration Word locations. A separate bit, WPCFG, is used to independently protect the last page of program space, including the Flash Configuration Words. Programming WPCFG (= 0) protects the last page regardless of the other bit settings. This may be useful in circumstances where write protection is needed for both a code segment in the bottom of memory, as well as the Flash Configuration Words. The various options for segment code protection are shown in Table 25-2.
25.4.3
CONFIGURATION REGISTER PROTECTION
The Configuration registers are protected against inadvertent or unwanted changes or reads in two ways. The primary protection method is the same as that of the RP registers - shadow registers contain a complimentary value which is constantly compared with the actual value. To safeguard against unpredictable events, Configuration bit changes resulting from individual cell level disruptions (such as ESD events) will cause a parity error and trigger a device Reset. The data for the Configuration registers is derived from the Flash Configuration Words in program memory. When the GCP bit is set, the source data for device configuration is also protected as a consequence. Even if General Segment protection is not enabled, the device configuration can be protected by using the appropriate code cement protection setting.
TABLE 25-2:
WPDIS 1 1 0
SEGMENT CODE PROTECTION CONFIGURATION OPTIONS
WPCFG 1 0 0 Write/Erase Protection of Code Segment No additional protection enabled; all program memory protection configured by GCP and GWRP Last code page protected, including Flash Configuration Words Addresses from first address of code page defined by WPFP8:WPFP0 through end of implemented program memory (inclusive) protected, including Flash Configuration Words Address 000000h through last address of code page defined by WPFP8:WPFP0 (inclusive) protected Addresses from first address of code page defined by WPFP8:WPFP0 through end of implemented program memory (inclusive) protected, including Flash Configuration Words Addresses from first address of code page defined by WPFP8:WPFP0 through end of implemented program memory (inclusive) protected
Segment Configuration Bits WPEND X X 1
0 0
0 1
0 1
0
0
1
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25.5 JTAG Interface 25.7 In-Circuit Debugger
PIC24FJ256GB110 family devices implement a JTAG interface, which supports boundary scan device testing as well as In-Circuit Serial Programming. When MPLAB(R) ICD 2 is selected as a debugger, the in-circuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE. Debugging functionality is controlled through the PGECx (Emulation/Debug Clock) and PGEDx (Emulation/Debug Data) pins. To use the in-circuit debugger function of the device, the design must implement ICSP connections to MCLR, VDD, VSS and the PGECx/PGEDx pin pair designated by the ICS Configuration bits. In addition, when the feature is enabled, some of the resources are not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins.
25.6
In-Circuit Serial Programming
PIC24FJ256GB110 family microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock (PGECx) and data (PGEDx) and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.
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26.0 DEVELOPMENT SUPPORT
26.1
The PIC(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer - PICkitTM 2 Development Programmer * Low-Cost Demonstration and Development Boards and Evaluation Kits
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Visual device initializer for easy register initialization * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.
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26.2 MPASM Assembler 26.5
The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
MPLAB ASM30 Assembler, Linker and Librarian
MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
26.6
MPLAB SIM Software Simulator
26.3
MPLAB C18 and MPLAB C30 C Compilers
The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip's PIC18 and PIC24 families of microcontrollers and the dsPIC30 and dsPIC33 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
26.4
MPLINK Object Linker/ MPLIB Object Librarian
The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
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26.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 26.9 MPLAB ICD 2 In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices.
The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows(R) 32-bit operating system were chosen to best make these features available in a simple, unified application.
26.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications.
26.8
MPLAB REAL ICE In-Circuit Emulator System
MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC(R) Flash MCUs and dsPIC(R) Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The MPLAB REAL ICE probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.
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26.11 PICSTART Plus Development Programmer
The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant.
26.13 Demonstration, Development and Evaluation Boards
A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.
26.12 PICkit 2 Development Programmer
The PICkitTM 2 Development Programmer is a low-cost programmer and selected Flash device debugger with an easy-to-use interface for programming many of Microchip's baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH's PICCTM Lite C compiler, and is designed to help get up to speed quickly using PIC(R) microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip's powerful, mid-range Flash memory family of microcontrollers.
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27.0
Note:
INSTRUCTION SET SUMMARY
This chapter is a brief summary of the PIC24F instruction set architecture, and is not intended to be a comprehensive reference source.
The literal instructions that involve data movement may use some of the following operands: * A literal value to be loaded into a W register or file register (specified by the value of `k') * The W register or file register where the literal value is to be loaded (specified by `Wb' or `f') However, literal instructions that involve arithmetic or logical operations use some of the following operands: * The first source operand which is a register `Wb' without any address modifier * The second source operand which is a literal value * The destination of the result (only if not the same as the first source operand) which is typically a register `Wd' with or without an address modifier The control instructions may use some of the following operands: * A program memory address * The mode of the table read and table write instructions All instructions are a single word, except for certain double-word instructions, which were made double-word instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are `0's. If this second word is executed as an instruction (by itself), it will execute as a NOP. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (unconditional/computed branch), indirect CALL/GOTO, all table reads and writes, and RETURN/RETFIE instructions, which are single-word instructions but take two or three cycles. Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. Moreover, double-word moves require two cycles. The double-word instructions execute in two instruction cycles.
The PIC24F instruction set adds many enhancements to the previous PIC(R) MCU instruction sets, while maintaining an easy migration from previous PIC MCU instruction sets. Most instructions are a single program memory word. Only three instructions require two program memory locations. Each single-word instruction is a 24-bit word divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: * * * * Word or byte-oriented operations Bit-oriented operations Literal operations Control operations
Table 27-1 shows the general symbols used in describing the instructions. The PIC24F instruction set summary in Table 27-2 lists all the instructions, along with the status flags affected by each instruction. Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands: * The first source operand which is typically a register `Wb' without any address modifier * The second source operand which is typically a register `Ws' with or without an address modifier * The destination of the result which is typically a register `Wd' with or without an address modifier However, word or byte-oriented file register instructions have two operands: * The file register specified by the value `f' * The destination, which could either be the file register `f' or the W0 register, which is denoted as `WREG' Most bit-oriented instructions (including rotate/shift instructions) have two operands: simple
* The W register (with or without an address modifier) or file register (specified by the value of `Ws' or `f') * The bit in the W register or file register (specified by a literal value or indirectly by the contents of register `Wb')
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TABLE 27-1:
Field #text (text) [text] {} .b .d .S .w bit4 C, DC, N, OV, Z Expr f lit1 lit4 lit5 lit8 lit10 lit14 lit16 lit23 None PC Slit10 Slit16 Slit6 Wb Wd Wdo Wm,Wn Wn Wnd Wns WREG Ws Wso Means literal defined by "text" Means "content of text" Means "the location addressed by text" Optional field or operation Register bit field Byte mode selection Double-Word mode selection Shadow register select Word mode selection (default) 4-bit bit selection field (used in word addressed instructions) {0...15} MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Absolute address, label or expression (resolved by the linker) File register address {0000h...1FFFh} 1-bit unsigned literal {0,1} 4-bit unsigned literal {0...15} 5-bit unsigned literal {0...31} 8-bit unsigned literal {0...255} 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode 14-bit unsigned literal {0...16383} 16-bit unsigned literal {0...65535} 23-bit unsigned literal {0...8388607}; LSB must be `0' Field does not require an entry, may be blank Program Counter 10-bit signed literal {-512...511} 16-bit signed literal {-32768...32767} 6-bit signed literal {-16...16} Base W register {W0..W15} Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Destination W register { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Dividend, Divisor working register pair (direct addressing) One of 16 working registers {W0..W15} One of 16 destination working registers {W0..W15} One of 16 source working registers {W0..W15} W0 (working register used in file register instructions) Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
SYMBOLS USED IN OPCODE DESCRIPTIONS
Description
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TABLE 27-2:
Assembly Mnemonic ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDC ADDC ADDC AND AND AND AND AND AND ASR ASR ASR ASR ASR ASR BCLR BRA BCLR BCLR BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BSET BSW BTG BTSC BSET BSET BSW.C BSW.Z BTG BTG BTSC BTSC f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f,#bit4 Ws,#bit4 C,Expr GE,Expr GEU,Expr GT,Expr GTU,Expr LE,Expr LEU,Expr LT,Expr LTU,Expr N,Expr NC,Expr NN,Expr NOV,Expr NZ,Expr OV,Expr Expr Z,Expr Wn f,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4
INSTRUCTION SET OVERVIEW
Assembly Syntax f = f + WREG WREG = f + WREG Wd = lit10 + Wd Wd = Wb + Ws Wd = Wb + lit5 f = f + WREG + (C) WREG = f + WREG + (C) Wd = lit10 + Wd + (C) Wd = Wb + Ws + (C) Wd = Wb + lit5 + (C) f = f .AND. WREG WREG = f .AND. WREG Wd = lit10 .AND. Wd Wd = Wb .AND. Ws Wd = Wb .AND. lit5 f = Arithmetic Right Shift f WREG = Arithmetic Right Shift f Wd = Arithmetic Right Shift Ws Wnd = Arithmetic Right Shift Wb by Wns Wnd = Arithmetic Right Shift Wb by lit5 Bit Clear f Bit Clear Ws Branch if Carry Branch if Greater than or Equal Branch if Unsigned Greater than or Equal Branch if Greater than Branch if Unsigned Greater than Branch if Less than or Equal Branch if Unsigned Less than or Equal Branch if Less than Branch if Unsigned Less than Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws Write Z bit to Ws Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Description # of Words 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 1 1 1 1 Status Flags Affected C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z N, Z N, Z N, Z N, Z N, Z C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z None None None None None None None None None None None None None None None None None None None None None None None None None None
1 None (2 or 3) 1 None (2 or 3)
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TABLE 27-2:
Assembly Mnemonic BTSS BTSS BTSS BTST BTST BTST.C BTST.Z BTST.C BTST.Z BTSTS BTSTS BTSTS.C BTSTS.Z CALL CLR CALL CALL CLR CLR CLR CLRWDT COM CLRWDT COM COM COM CP CP CP CP CP0 CPB CP0 CP0 CPB CPB CPB CPSEQ CPSGT CPSLT CPSNE DAW DEC CPSEQ CPSGT CPSLT CPSNE DAW DEC DEC DEC DEC2 DEC2 DEC2 DEC2 DISI DIV DISI DIV.SW DIV.SD DIV.UW DIV.UD EXCH FF1L FF1R EXCH FF1L FF1R f f,WREG Ws,Wd f Wb,#lit5 Wb,Ws f Ws f Wb,#lit5 Wb,Ws Wb,Wn Wb,Wn Wb,Wn Wb,Wn Wn f f,WREG Ws,Wd f f,WREG Ws,Wd #lit14 Wm,Wn Wm,Wn Wm,Wn Wm,Wn Wns,Wnd Ws,Wnd Ws,Wnd
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly Syntax f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 Ws,#bit4 lit23 Wn f WREG Ws Description Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Ws to C Bit Test Ws to Z Bit Test Ws to C Bit Test Ws to Z Bit Test then Set f Bit Test Ws to C, then Set Bit Test Ws to Z, then Set Call Subroutine Call Indirect Subroutine f = 0x0000 WREG = 0x0000 Ws = 0x0000 Clear Watchdog Timer f=f WREG = f Wd = Ws Compare f with WREG Compare Wb with lit5 Compare Wb with Ws (Wb - Ws) Compare f with 0x0000 Compare Ws with 0x0000 Compare f with WREG, with Borrow Compare Wb with lit5, with Borrow Compare Wb with Ws, with Borrow (Wb - Ws - C) Compare Wb with Wn, Skip if = Compare Wb with Wn, Skip if > Compare Wb with Wn, Skip if < Compare Wb with Wn, Skip if Wn = Decimal Adjust Wn f = f -1 WREG = f -1 Wd = Ws - 1 f=f-2 WREG = f - 2 Wd = Ws - 2 Disable Interrupts for k Instruction Cycles Signed 16/16-bit Integer Divide Signed 32/16-bit Integer Divide Unsigned 16/16-bit Integer Divide Unsigned 32/16-bit Integer Divide Swap Wns with Wnd Find First One from Left (MSb) Side Find First One from Right (LSb) Side # of Words 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles Status Flags Affected
1 None (2 or 3) 1 None (2 or 3) 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Z C Z C Z Z C Z None None None None None WDTO, Sleep N, Z N, Z N, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z
1 None (2 or 3) 1 None (2 or 3) 1 None (2 or 3) 1 None (2 or 3) 1 1 1 1 1 1 1 1 18 18 18 18 1 1 1 C C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None N, Z, C, OV N, Z, C, OV N, Z, C, OV N, Z, C, OV None C C
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TABLE 27-2:
Assembly Mnemonic GOTO INC GOTO GOTO INC INC INC INC2 INC2 INC2 INC2 IOR IOR IOR IOR IOR IOR LNK LSR LNK LSR LSR LSR LSR LSR MOV MOV MOV MOV MOV MOV MOV.b MOV MOV MOV MOV MOV.D MOV.D MUL MUL.SS MUL.SU MUL.US MUL.UU MUL.SU MUL.UU MUL NEG NEG NEG NEG NOP POP NOP NOPR POP POP POP.D POP.S PUSH PUSH PUSH PUSH.D PUSH.S f Wso Wns f Wdo Wnd
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly Syntax Expr Wn f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd #lit14 f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f,Wn [Wns+Slit10],Wnd f f,WREG #lit16,Wn #lit8,Wn Wn,f Wns,[Wns+Slit10] Wso,Wdo WREG,f Wns,Wd Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,#lit5,Wnd Wb,#lit5,Wnd f f f,WREG Ws,Wd Go to Address Go to Indirect f=f+1 WREG = f + 1 Wd = Ws + 1 f=f+2 WREG = f + 2 Wd = Ws + 2 f = f .IOR. WREG WREG = f .IOR. WREG Wd = lit10 .IOR. Wd Wd = Wb .IOR. Ws Wd = Wb .IOR. lit5 Link Frame Pointer f = Logical Right Shift f WREG = Logical Right Shift f Wd = Logical Right Shift Ws Wnd = Logical Right Shift Wb by Wns Wnd = Logical Right Shift Wb by lit5 Move f to Wn Move [Wns+Slit10] to Wnd Move f to f Move f to WREG Move 16-bit Literal to Wn Move 8-bit Literal to Wn Move Wn to f Move Wns to [Wns+Slit10] Move Ws to Wd Move WREG to f Move Double from W(ns):W(ns+1) to Wd Move Double from Ws to W(nd+1):W(nd) {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) {Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws) {Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws) {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws) {Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5) {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5) W3:W2 = f * WREG f=f+1 WREG = f + 1 Wd = Ws + 1 No Operation No Operation Pop f from Top-of-Stack (TOS) Pop from Top-of-Stack (TOS) to Wdo Pop from Top-of-Stack (TOS) to W(nd):W(nd+1) Pop Shadow Registers Push f to Top-of-Stack (TOS) Push Wso to Top-of-Stack (TOS) Push W(ns):W(ns+1) to Top-of-Stack (TOS) Push Shadow Registers Description # of Words 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 2 1 None N, Z None None None None None None None None None C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None None None None None All None None None None Status Flags Affected None None C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z N, Z N, Z N, Z N, Z N, Z None C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z None None N, Z N, Z None None None
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TABLE 27-2:
Assembly Mnemonic PWRSAV RCALL REPEAT RESET RETFIE RETLW RETURN RLC PWRSAV RCALL RCALL REPEAT REPEAT RESET RETFIE RETLW RETURN RLC RLC RLC RLNC RLNC RLNC RLNC RRC RRC RRC RRC RRNC RRNC RRNC RRNC SE SETM SE SETM SETM SETM SL SL SL SL SL SL SUB SUB SUB SUB SUB SUB SUBB SUBB SUBB SUBB SUBB SUBB SUBR SUBR SUBR SUBR SUBR SUBBR SUBBR SUBBR SUBBR SUBBR SWAP SWAP.b SWAP f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG Ws,Wd Ws,Wnd f WREG Ws f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd Wn Wn #lit10,Wn
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly Syntax #lit1 Expr Wn #lit14 Wn Description Go into Sleep or Idle mode Relative Call Computed Call Repeat Next Instruction lit14 + 1 times Repeat Next Instruction (Wn) + 1 times Software Device Reset Return from Interrupt Return with Literal in Wn Return from Subroutine f = Rotate Left through Carry f WREG = Rotate Left through Carry f Wd = Rotate Left through Carry Ws f = Rotate Left (No Carry) f WREG = Rotate Left (No Carry) f Wd = Rotate Left (No Carry) Ws f = Rotate Right through Carry f WREG = Rotate Right through Carry f Wd = Rotate Right through Carry Ws f = Rotate Right (No Carry) f WREG = Rotate Right (No Carry) f Wd = Rotate Right (No Carry) Ws Wnd = Sign-Extended Ws f = FFFFh WREG = FFFFh Ws = FFFFh f = Left Shift f WREG = Left Shift f Wd = Left Shift Ws Wnd = Left Shift Wb by Wns Wnd = Left Shift Wb by lit5 f = f - WREG WREG = f - WREG Wn = Wn - lit10 Wd = Wb - Ws Wd = Wb - lit5 f = f - WREG - (C) WREG = f - WREG - (C) Wn = Wn - lit10 - (C) Wd = Wb - Ws - (C) Wd = Wb - lit5 - (C) f = WREG - f WREG = WREG - f Wd = Ws - Wb Wd = lit5 - Wb f = WREG - f - (C) WREG = WREG - f - (C) Wd = Ws - Wb - (C) Wd = lit5 - Wb - (C) Wn = Nibble Swap Wn Wn = Byte Swap Wn # of Words 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 1 2 2 1 1 1 3 (2) 3 (2) 3 (2) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Status Flags Affected WDTO, Sleep None None None None None None None None C, N, Z C, N, Z C, N, Z N, Z N, Z N, Z C, N, Z C, N, Z C, N, Z N, Z N, Z N, Z C, N, Z None None None C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None None
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TABLE 27-2:
Assembly Mnemonic TBLRDH TBLRDL TBLWTH TBLWTL ULNK XOR TBLRDH TBLRDL TBLWTH TBLWTL ULNK XOR XOR XOR XOR XOR ZE ZE f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd Ws,Wnd
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly Syntax Ws,Wd Ws,Wd Ws,Wd Ws,Wd Description Read Prog<23:16> to Wd<7:0> Read Prog<15:0> to Wd Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink Frame Pointer f = f .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR. Wd Wd = Wb .XOR. Ws Wd = Wb .XOR. lit5 Wnd = Zero-Extend Ws # of Words 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 2 2 2 2 1 1 1 1 1 1 1 Status Flags Affected None None None None None N, Z N, Z N, Z N, Z N, Z C, Z, N
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NOTES:
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28.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC24FJ256GB110 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24FJ256GB110 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings()
Ambient temperature under bias.............................................................................................................-40C to +100C Storage temperature .............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V) Voltage on any digital only pin with respect to VSS .................................................................................. -0.3V to +6.0V Voltage on VDDCORE with respect to VSS ................................................................................................. -0.3V to +3.0V Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin (Note 1)................................................................................................................250 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports (Note 1)....................................................................................................200 mA Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 28-1). NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
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28.1 DC Characteristics
PIC24FJ256GB110 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
3.00V 2.75V Voltage (VDDCORE)(1) 2.50V 2.25V 2.00V PIC24FJXXXGB1XX 2.25V 2.75V
FIGURE 28-1:
16 MHz
Frequency
32 MHz
For frequencies between 16 MHz and 32 MHz, FMAX = (64 MHz/V) * (VDDCORE - 2V) + 16 MHz. Note 1: When the voltage regulator is disabled, VDD and VDDCORE must be maintained so that VDDCORE VDD 3.6V.
TABLE 28-1:
THERMAL OPERATING CONDITIONS
Rating Symbol TJ TA Min -40 -40 Typ -- -- Max +125 +85 Unit C C
PIC24FJ256GB110 family: Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD - IOH) I/O Pin Power Dissipation: PI/O = ({VDD - VOH} x IOH) + (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJ - TA)/JA W
PD
PINT + PI/O
W
TABLE 28-2:
THERMAL PACKAGING CHARACTERISTICS
Characteristic Symbol JA JA JA Typ 50.0 69.4 76.6 Max -- -- -- Unit C/W C/W C/W Notes (Note 1) (Note 1) (Note 1)
Package Thermal Resistance, 14x14x1 mm TQFP Package Thermal Resistance, 12x12x1 mm TQFP Package Thermal Resistance, 10x10x1 mm TQFP Note 1:
Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
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TABLE 28-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param Symbol No. Operating Voltage DC10 Supply Voltage VDD VDD VDDCORE DC12 DC16 VDR VPOR RAM Data Retention Voltage(2) VDD Start VoltAge To ensure internal Power-on Reset Signal VDD Rise Rate to Ensure Internal Power-on Reset Signal 2.2 VDDCORE 2.0 1.5 -- -- -- -- -- VSS 3.6 3.6 2.75 -- -- V V V V V Regulator enabled Regulator disabled Regulator disabled Characteristic
DC17
SVDD
.05
--
--
V/ms
0-3.3V in 0.1s 0-2.5V in 60 ms
Note 1: 2:
Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data.
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TABLE 28-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. DC20 DC20a DC20b DC20d DC20e DC20f DC23 DC23a DC23b DC23d DC23e DC23f DC24 DC24a DC24b DC24d DC24e DC24f DC31 DC31a DC31b DC31d DC31e DC31f Note 1: 2: Typical(1)
Operating Current (IDD)(2) 0.83 0.83 0.83 1.1 1.1 1.1 3.3 3.3 3.3 4.3 4.3 4.3 18.2 18.2 18.2 18.2 18.2 18.2 15.0 15.0 20.0 57.0 57.0 95.0 1.2 1.2 1.2 1.6 1.6 1.6 4.3 4.3 4.3 6 6 6 24 24 24 24 24 24 20 20 26 75 75 124 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA A A A A A A -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C 3.3V(4) 2.0V(3) LPRC (31 kHz) 3.3V(4) 2.5V(3) 16 MIPS 3.3V(4) 2.0V(3) 4 MIPS 3.3V(4) 2.0V(3) 1 MIPS
3: 4:
Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set. On-chip voltage regulator disabled (ENVREG tied to VSS). On-chip voltage regulator enabled (ENVREG tied to VDD). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled.
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TABLE 28-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. DC40 DC40a DC40b DC40d DC40e DC40f DC43 DC43a DC43b DC43d DC43e DC43f DC47 DC47a DC47b DC47c DC47d DC47e DC50 DC50a DC50b DC50d DC50e DC50f DC51 DC51a DC51b DC51d DC51e DC51f Note 1: 2: Typical(1)
Idle Current (IIDLE)(2) 220 220 220 300 300 300 0.85 0.85 0.87 1.1 1.1 1.1 4.4 4.4 4.4 4.4 4.4 4.4 1.1 1.1 1.1 1.4 1.4 1.4 4.3 4.5 7.2 38 44 70 290 290 290 390 390 420 1.1 1.1 1.2 1.4 1.4 1.4 5.6 5.6 5.6 5.6 5.6 5.6 1.4 1.4 1.4 1.8 1.8 1.8 6.0 6.0 25 50 60 110 A A A A A A mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA A A A A A A -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C 3.3V(4) 2.0V(3) LPRC (31 kHz) 3.3V(4) 2.0V(3) FRC (4 MIPS) 3.3V(4) 2.5V(3) 16 MIPS 3.3V(4) 2.0V(3) 4 MIPS 3.3V(4) 2.0V(3) 1 MIPS
3: 4:
Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IIDLE current is measured with the core off, OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set. On-chip voltage regulator disabled (ENVREG tied to VSS). On-chip voltage regulator enabled (ENVREG tied to VDD). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled.
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TABLE 28-6: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. DC60 DC60a DC60b DC60c DC60d DC60e DC60f DC60g DC60h DC61 DC61a DC61b DC61c DC61d DC61e DC61f DC61g DC61h DC62 DC62a DC62b DC62c DC62d DC62e DC62f DC62g DC62h Note 1: 2: Typical(1)
Power-Down Current (IPD)(2) 0.1 0.15 3.7 0.2 0.25 4.2 3.6 4.0 11.0 1.75 1.75 1.75 2.4 2.4 2.4 2.8 2.8 2.8 2.5 2.5 3.0 2.8 3.0 3.0 3.5 3.5 4.0 1 1 18 1.3 1.3 27 9 10 36 3 3 3 4 4 4 5 5 5 7 7 7 7 7 7 10 10 10 A A A A A A A A A A A A A A A A A A A A A A A A A A A -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C 3.3V(4) 2.5V(3) RTCC + Timer1 w/32 kHz Crystal: RTCC + ITI32(5) 2.0V(3) 3.3V(4) 2.5V(3) Watchdog Timer Current: IWDT(5) 2.0V(3) 3.3V(4) 2.5V(3) Base Power-Down Current(5) 2.0V(3)
3: 4: 5:
Data in the Typical column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled high. WDT, etc., are all switched off, VREGS bit is clear, and the Peripheral Module Disable (PMD) bits for all unused peripherals are set. On-chip voltage regulator disabled (ENVREG tied to VSS). On-chip voltage regulator enabled (ENVREG tied to VDD). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled. The current is the additional current consumed when the module is enabled. This current should be added to the base IPD current.
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TABLE 28-7: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param No. DI10 DI11 DI15 DI16 DI17 DI18 DI19 VIH DI20 Sym VIL Characteristic Input Low Voltage(4) I/O Pins with ST Buffer I/O Pins with TTL Buffer MCLR OSC1 (XT mode) OSC1 (HS mode) I/O Pins with I2CTM Buffer: I/O Pins with SMBus Buffer: Input High Voltage(4) I/O Pins with ST Buffer: with Analog Functions, Digital Only I/O Pins with TTL Buffer: with Analog Functions, Digital Only MCLR OSC1 (XT mode) OSC1 (HS mode) I/O Pins with I2C Buffer: with Analog Functions, Digital Only I/O Pins with SMBus Buffer: with Analog Functions, Digital Only ICNPU CNxx Pull-up Current IIL DI50 DI51 DI55 DI56 Note 1: 2: Input Leakage I/O Ports Analog Input Pins MCLR OSC1 Current(2,3) -- -- -- -- -- -- -- -- +1 +1 +1 +1 A A A A VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD VSS VPIN VDD, XT and HS modes 0.8 VDD 0.8 VDD 0.25 VDD + 0.8 0.25 VDD + 0.8 0.8 VDD 0.7 VDD 0.7 VDD 0.7 VDD 0.7 VDD 2.1 2.1 50 250 -- -- -- -- -- -- -- -- -- VDD 5.5 VDD 5.5 VDD VDD VDD VDD 5.5 VDD 5.5 400 V V V V V V V V V 2.5V VPIN VDD V V A VDD = 3.3V, VPIN = VSS VSS VSS VSS VSS VSS VSS VSS -- -- -- -- -- -- -- 0.2 VDD 0.15 VDD 0.2 VDD 0.2 VDD 0.2 VDD 0.3 VDD 0.8 V V V V V V V SMBus enabled
DI21
DI25 DI26 DI27 DI28
DI29
DI30
3: 4:
Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Refer to Table 1-4 for I/O pins buffer types.
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TABLE 28-8: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param No. DO10 DO16 VOH DO20 Sym VOL Characteristic Output Low Voltage I/O Ports OSC2/CLKO Output High Voltage I/O Ports 3.0 2.4 1.65 1.4 DO26 Note 1: OSC2/CLKO 2.4 1.4 -- -- -- -- -- -- -- -- -- -- -- -- V V V V V V IOH = -3.0 mA, VDD = 3.6V IOH = -6.0 mA, VDD = 3.6V IOH = -1.0 mA, VDD = 2.0V IOH = -3.0 mA, VDD = 2.0V IOH = -6.0 mA, VDD = 3.6V IOH = -3.0 mA, VDD = 2.0V -- -- -- -- -- -- -- -- 0.4 0.4 0.4 0.4 V V V V IOL = 8.5 mA, VDD = 3.6V IOL = 6.0 mA, VDD = 2.0V IOL = 8.5 mA, VDD = 3.6V IOL = 6.0 mA, VDD = 2.0V
Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested.
TABLE 28-9:
DC CHARACTERISTICS: PROGRAM MEMORY
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ(1) Max Units Conditions
DC CHARACTERISTICS Param No. D130 D131 D132B D133A D133B D134 D135 Note 1: Sym Characteristic Program Flash Memory EP VPR TIW TIE Cell Endurance VDD for Read Self-Timed Write Cycle Time Self-Timed Page Erase Time
10000 VMIN 2.25 -- 40 20 --
-- -- -- 3 -- -- 7
-- 3.6 3.6 -- -- -- --
E/W V V ms ms Year mA
-40C to +85C VMIN = Minimum operating voltage VMIN = Minimum operating voltage
VPEW VDD for Self-Timed Write
TRETD Characteristic Retention IDDP Supply Current during Programming
Provided no other specifications are violated
Data in "Typ" column is at 3.3V, 25C unless otherwise stated.
TABLE 28-10: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: -40C < TA < +85C (unless otherwise stated) Param Symbol No. VRGOUT CEFC Characteristics Regulator Output Voltage External Filter Capacitor Value Min -- 4.7 Typ 2.5 10 Max -- -- Units V F Series resistance < 3 Ohm recommended; < 5 Ohm required. ENVREG tied to VDD ENVREG tied to VSS Comments
TVREG TPWRT
-- --
50 64
-- --
s ms
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28.2 AC Characteristics and Timing Parameters
The information contained in this section defines the PIC24FJ256GB110 family AC characteristics and timing parameters.
TABLE 28-11: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
AC CHARACTERISTICS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Operating voltage VDD range as described in Section 28.1 "DC Characteristics".
FIGURE 28-2:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 2 - for OSCO
Load Condition 1 - for all pins except OSCO VDD/2 RL
Pin VSS
CL
Pin VSS
CL
RL = 464 CL = 50 pF for all pins except OSCO 15 pF for OSCO output
TABLE 28-12: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param Symbol No. DO50 COSC2 Characteristic OSCO/CLKO pin Min -- Typ(1) -- Max 15 Units pF Conditions In XT and HS modes when external clock is used to drive OSCI. EC mode. In I2CTM mode.
DO56 DO58 Note 1:
CIO CB
All I/O pins and OSCO SCLx, SDAx
-- --
-- --
50 400
pF pF
Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested.
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FIGURE 28-3:
Q4
EXTERNAL CLOCK TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
OSCI
OS20 OS25 OS30 OS30 OS31 OS31
CLKO
OS40 OS41
TABLE 28-13: EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS Param Sym No. OS10 Characteristic Standard Operating Conditions: 2.50 to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min DC 4 3 4 10 10 31 -- 62.5 0.45 x TOSC -- -- -- Typ(1) -- -- -- -- -- -- -- -- -- -- -- 6 6 Max 32 48 10 8 32 32 33 -- DC -- 20 10 10 Units MHz MHz MHz MHz MHz MHz kHz -- ns ns ns ns ns EC EC EC ECPLL XT XTPLL HS HSPLL SOSC See parameter OS10 for FOSC value Conditions
FOSC External CLKI Frequency (External clocks allowed only in EC mode) Oscillator Frequency
OS20 OS25 OS30 OS31 OS40 OS41
TOSC TOSC = 1/FOSC TCY Instruction Cycle Time(2)
TosL, External Clock in (OSCI) TosH High or Low Time TosR, External Clock in (OSCI) TosF Rise or Fall Time TckR TckF CLKO Rise Time(3) CLKO Fall Time(3)
Note 1: 2:
3:
Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "Min." values with an external clock applied to the OSCI/CLKI pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).
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TABLE 28-14: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.0V TO 3.6V)
AC CHARACTERISTICS Param No. OS50 OS51 OS52 OS53 Note 1: 2: Sym FPLLI FSYS Characteristic(1) PLL Input Frequency Range(2) PLL Output Frequency Range Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min 4 95.76 -- -0.25 Typ(2) -- -- -- -- Max 32 96.24 200 0.25 Units MHz MHz s % Conditions ECPLL, HSPLL, XTPLL modes
TLOCK PLL Start-up Time (Lock Time) DCLK CLKO Stability (Jitter)
These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested.
TABLE 28-15: AC CHARACTERISTICS: INTERNAL RC ACCURACY
AC CHARACTERISTICS Param No. F20 Note 1: FRC Characteristic Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ Max Units Conditions
Internal FRC Accuracy @ 8 MHz(1) -2 -5 -- -- 2 5 % % +25C -40C TA +85C 3.0V VDD 3.6V 3.0V VDD 3.6V
Frequency calibrated at 25C and 3.3V. OSCTUN bits can be used to compensate for temperature drift.
TABLE 28-16: INTERNAL RC ACCURACY
AC CHARACTERISTICS Param No. F21 Note 1: Characteristic LPRC @ 31 kHz(1) -20 -- 20 % -40C TA +85C 3.0V VDD 3.6V Change of LPRC frequency as VDD changes. Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ Max Units Conditions
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FIGURE 28-4: CLKO AND I/O TIMING CHARACTERISTICS
I/O Pin (Input) DI35 DI40 I/O Pin (Output) Old Value DO31 DO32 Note: Refer to Figure 28-2 for load conditions. New Value
TABLE 28-17: CLKO AND I/O TIMING REQUIREMENTS
AC CHARACTERISTICS Param No. DO31 DO32 DI35 DI40 Note 1: Sym TIOR TIOF TINP TRBP Characteristic Port Output Rise Time Port Output Fall Time INTx pin High or Low Time (output) CNx High or Low Time (input) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min -- -- 20 2 Typ(1) 10 10 -- -- Max 25 25 -- -- Units ns ns ns TCY Conditions
Data in "Typ" column is at 3.3V, 25C unless otherwise stated.
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TABLE 28-18: ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS Param No. AD01 Symbol Characteristic Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min. Typ Max. Units Conditions
Device Supply AVDD Module VDD Supply Greater of VDD - 0.3 or 2.0 VSS - 0.3 AVSS + 1.7 AVSS AVSS - 0.3 -- Lesser of VDD + 0.3 or 3.6 VSS + 0.3 AVDD AVDD - 1.7 AVDD + 0.3 V
AD02 AD05 AD06 AD07
AVSS VREFH VREFL VREF
Module VSS Supply Reference Voltage High Reference Voltage Low Absolute Reference Voltage
-- -- -- --
V V V V
Reference Inputs
Analog Input AD10 AD11 AD12 AD13 VINH-VINL Full-Scale Input Span VIN VINL -- Absolute Input Voltage Absolute VINL Input Voltage Leakage Current VREFL AVSS - 0.3 AVSS - 0.3 -- 0.00 1 -- -- -- VREFH AVDD + 0.3 AVDD/2 0.610 V V V A VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V, Source Impedance = 2.5 k 10-bit (Note 2) --
AD17
RIN
Recommended Impedance of Analog Voltage Source Resolution Integral Nonlinearity Differential Nonlinearity Gain Error Offset Error Monotonicity(1)
--
2.5K
ADC Accuracy AD20b Nr AD21b INL AD22b DNL AD23b GERR AD24b EOFF AD25b -- Note 1: 2: -- -- -- -- -- -- 10 1 0.5 1 1 -- -- <2 <1 3 2 -- bits LSb LSb LSb LSb -- VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V Guaranteed
The ADC conversion result never decreases with an increase in the input voltage and has no missing codes. Measurements taken with external VREF+ and VREF- used as the ADC voltage reference.
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TABLE 28-19: ADC CONVERSION TIMING REQUIREMENTS(1)
AC CHARACTERISTICS Param No. AD50 AD51 Symbol Characteristic Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min. Typ Max. Units Conditions
Clock Parameters TAD tRC ADC Clock Period ADC Internal RC Oscillator Period Conversion Time Throughput Rate Sample Time Sample Start Delay from setting Sample bit (SAMP) 75 -- -- 250 -- -- ns ns TCY = 75 ns, AD1CON3 in default state
Conversion Rate AD55 AD56 AD57 AD61 Note 1: tCONV FCNV tSAMP tPSS -- -- -- Clock Parameters 2 -- 3 TAD 12 -- 1 -- 500 -- TAD ksps TAD AVDD > 2.7V
Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures.
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29.0
29.1
PACKAGING INFORMATION
Package Marking Information
64-Lead TQFP (10x10x1 mm) Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 80-Lead TQFP (12x12x1 mm)
PIC24FJ256 GB106-I/ PT e3 0820017 Example
XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
PIC24FJ256GB 108-I/PT e3 0820017
100-Lead TQFP (12x12x1 mm)
Example
XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
PIC24FJ256GB 110-I/PT e3 0820017
100-Lead TQFP (14x14x1 mm)
Example
XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
PIC24FJ256GB 110-I/PF e3 0820017
Legend: XX...X Y YY WW NNN
e3
* Note:
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
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29.2 Package Details
The following sections give the technical details of the packages.
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APPENDIX A: REVISION HISTORY
Revision A (October 2007)
Original data sheet for the PIC24FJ256GB110 family of devices.
Revision B (March 2008)
Changes to Section 28.0 "Electrical Characteristics" and minor edits to text throughout document.
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INDEX
A
A/D Converter Analog Input Model ................................................... 257 Transfer Function...................................................... 258 AC Characteristics ADC Conversion Timing ........................................... 306 CLKO and I/O Timing................................................ 304 AC Characteristics Internal RC Accuracy ................................................ 303 Alternate Interrupt Vector Table (AIVT) .............................. 67 Assembler MPASM Assembler................................................... 282 PSV Operation............................................................ 54 Reset System ............................................................. 61 RTCC........................................................................ 235 Shared I/O Port Structure ......................................... 121 SPI Master, Frame Master Connection .................... 177 SPI Master, Frame Slave Connection ...................... 177 SPI Master/Slave Connection (Enhanced Buffer Modes)................................. 176 SPI Master/Slave Connection (Standard Mode)............................................... 176 SPI Slave, Frame Master Connection ...................... 177 SPI Slave, Frame Slave Connection ........................ 177 SPIx Module (Enhanced Mode)................................ 171 SPIx Module (Standard Mode) ................................. 170 System Clock Diagram ............................................. 109 Triple Comparator Module........................................ 259 UART (Simplified)..................................................... 187 USB OTG Interrupt Funnel ....................................... 201 USB OTG Module..................................................... 196 USB PLL................................................................... 116 USB Voltage Generation and Connections .............. 200 Watchdog Timer (WDT)............................................ 277
B
Block Diagram CRC Shifter Details................................................... 245 Block Diagrams 10-Bit High-Speed A/D Converter............................. 250 16-Bit Asynchronous Timer3 and Timer5 ................. 151 16-Bit Synchronous Timer2 and Timer4 ................... 151 16-Bit Timer1 Module................................................ 147 32-Bit Timer2/3 and Timer4/5 ................................... 150 Accessing Program Space Using Table Operations ................................................ 53 Addressable PMP Example ...................................... 232 Addressing for Table Registers................................... 55 BDT Mapping for Endpoint Buffering Modes ............ 197 CALL Stack Frame...................................................... 51 Comparator Voltage Reference ................................ 263 CPU Programmer's Model .......................................... 27 CRC Generator Configured for Polynomial............... 246 CTMU Connections and Internal Configuration for Capacitance Measurement.......................... 265 CTMU Typical Connections and Internal Configuration for Pulse Delay Generation ........ 266 CTMU Typical Connections and Internal Configuration for Time Measurement ............... 266 Data Access From Program Space Address Generation ............................................ 52 I2C Module ................................................................ 180 Individual Comparator Configuration ........................ 260 Input Capture ............................................................ 155 LCD Control .............................................................. 234 Legacy PMP Example............................................... 232 On-Chip Regulator Connections ............................... 275 Output Compare (16-Bit Mode)................................. 160 Output Compare (Double-Buffered 16-Bit PWM Mode) ........................................... 162 PCI24FJ256GB110 Family (General) ......................... 14 PIC24F CPU Core ...................................................... 26 PMP 8-Bit Multiplexed Address and Data Application................................................ 234 PMP EEPROM (8-Bit Data) ...................................... 234 PMP Master Mode, Demultiplexed Addressing ........................................................ 232 PMP Master Mode, Fully Multiplexed Addressing ........................................................ 233 PMP Master Mode, Partially Multiplexed Addressing ........................................................ 233 PMP Module Overview ............................................. 225 PMP Multiplexed Addressing .................................... 233 PMP Parallel EEPROM (16-Bit Data) ....................... 234 PMP Partially Multiplexed Addressing ...................... 233
C
C Compilers MPLAB C18.............................................................. 282 MPLAB C30.............................................................. 282 Charge Time Measurement Unit. See CTMU. Code Examples Basic Clock Switching Example ............................... 115 Configuring UART1 Input and Output Functions (PPS) ............................................... 127 Erasing a Program Memory Block.............................. 58 I/O Port Read/Write .................................................. 122 Initiating a Programming Sequence ........................... 59 Loading the Write Buffers ........................................... 59 Single-Word Flash Programming ............................... 60 Code Protection ................................................................ 277 Code Segment Protection ........................................ 277 Configuration Options....................................... 278 Configuration Protection ........................................... 278 Configuration Bits ............................................................. 269 Core Features....................................................................... 9 CPU Arithmetic Logic Unit (ALU) ........................................ 29 Control Registers........................................................ 28 Core Registers............................................................ 27 Programmer's Model .................................................. 25 CRC Setup Example ......................................................... 245 User Interface ........................................................... 246 CTMU Measuring Capacitance............................................ 265 Measuring Time........................................................ 266 Pulse Delay and Generation..................................... 266 Customer Change Notification Service............................. 323 Customer Notification Service .......................................... 323 Customer Support............................................................. 323
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D
Data Memory Address Space............................................................ 33 Memory Map ............................................................... 33 Near Data Space ........................................................ 34 SFR Space.................................................................. 34 Software Stack ............................................................ 51 Space Organization .................................................... 34 DC Characteristics I/O Pin Input Specifications ....................................... 299 I/O Pin Output Specifications .................................... 300 Program Memory ...................................................... 300 Development Support ....................................................... 281 Device Features (Summary) 100-Pin........................................................................ 13 64-Pin.......................................................................... 11 80-Pin.......................................................................... 12 Doze Mode........................................................................ 120 I2C Clock Rates .............................................................. 181 Reserved Addresses ................................................ 181 Setting Baud Rate as Bus Master............................. 181 Slave Address Masking ............................................ 181 Idle Mode .......................................................................... 120 Input Capture 32-Bit Mode .............................................................. 156 Synchronous and Trigger Modes.............................. 155 Input Capture with Dedicated Timers ............................... 155 Instruction Set Overview................................................................... 287 Summary .................................................................. 285 Instruction-Based Power-Saving Modes................... 119, 120 Inter-Integrated Circuit. See I2C. ...................................... 179 Internet Address ............................................................... 323 Interrupt Vector Table (IVT) ................................................ 67 Interrupts and Reset Sequence .................................................. 67 Control and Status Registers...................................... 70 Implemented Vectors.................................................. 69 Setup and Service Procedures ................................. 108 Trap Vectors ............................................................... 68 Vector Table ............................................................... 68 IrDA Support ..................................................................... 189
E
Electrical Characteristics A/D Specifications ..................................................... 305 Absolute Maximum Ratings ...................................... 293 Current Specifications ....................................... 296-298 External Clock ........................................................... 302 Load Conditions and Requirements for Specifications.................................................... 301 PLL Clock Specifications .......................................... 303 Thermal Conditions ................................................... 294 V/F Graph ................................................................. 294 Voltage Regulator Specifications .............................. 300 Voltage Specifications............................................... 295 Electrical Characteristics Internal RC Accuracy ................................................ 303 ENVREG Pin..................................................................... 275 Equations A/D Conversion Clock Period ................................... 257 Baud Rate Reload Calculation .................................. 181 Calculating the PWM Period ..................................... 163 Calculation for Maximum PWM Resolution............... 163 Relationship Between Device and SPI Clock Speed............................................... 178 RTCC Calibration ...................................................... 243 UART Baud Rate with BRGH = 0 ............................. 188 Errata .................................................................................... 7
J
JTAG Interface.................................................................. 279
M
Microchip Internet Web Site.............................................. 323 MPLAB ASM30 Assembler, Linker, Librarian ................... 282 MPLAB ICD 2 In-Circuit Debugger ................................... 283 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator .................................... 283 MPLAB Integrated Development Environment Software .............................................. 281 MPLAB PM3 Device Programmer .................................... 283 MPLAB REAL ICE In-Circuit Emulator System ................ 283 MPLINK Object Linker/MPLIB Object Librarian ................ 282
N
Near Data Space ................................................................ 34
O
Oscillator Configuration Clock Selection ......................................................... 110 Clock Switching ........................................................ 114 Sequence ......................................................... 115 Initial Configuration on POR ..................................... 110 USB Operation ......................................................... 116 Special Considerations..................................... 117 Output Compare 32-Bit Mode .............................................................. 159 Synchronous and Trigger Modes.............................. 159 Output Compare with Dedicated Timers........................... 159
F
Flash Configuration Words.................................. 32, 269-273 Flash Program Memory....................................................... 55 and Table Instructions................................................. 55 Enhanced ICSP Operation.......................................... 56 JTAG Operation .......................................................... 56 Programming Algorithm .............................................. 58 RTSP Operation.......................................................... 56 Single-Word Programming.......................................... 60
I
I/O Ports Analog Port Pins Configuration ................................. 122 Input Change Notification.......................................... 122 Open-Drain Configuration ......................................... 122 Parallel (PIO) ............................................................ 121 Peripheral Pin Select ................................................ 123 Pull-ups and Pull-downs ........................................... 122
P
Packaging ......................................................................... 307 Details....................................................................... 308 Marking ..................................................................... 307 Parallel Master Port. See PMP. ........................................ 225 Peripheral Enable bits....................................................... 120 Peripheral Module Disable bits ......................................... 120
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Peripheral Pin Select (PPS) .............................................. 123 Available Peripherals and Pins ................................. 123 Configuration Control ................................................ 126 Considerations for Use ............................................. 127 Input Mapping ........................................................... 124 Mapping Exceptions.................................................. 126 Output Mapping ........................................................ 125 Peripheral Priority ..................................................... 123 Registers........................................................... 128-146 PICSTART Plus Development Programmer ..................... 284 Pinout Descriptions ....................................................... 15-23 POR and On-Chip Voltage Regulator................................ 275 Power-Saving Clock Frequency and Clock Switching...................... 119 Power-Saving Features .................................................... 119 Power-up Requirements ................................................... 276 Product Identification System ........................................... 325 Program Memory Access Using Table Instructions................................. 53 Address Construction.................................................. 51 Address Space............................................................ 31 Flash Configuration Words ......................................... 32 Memory Maps ............................................................. 31 Organization................................................................ 32 Program Space Visibility ............................................. 54 Program Space Visibility (PSV) .......................................... 54 Pulse-Width Modulation (PWM) Mode .............................. 162 Pulse-Width Modulation. See PWM. PWM Duty Cycle and Period .............................................. 163 Registers AD1CHS0 (A/D Input Select).................................... 254 AD1CON1 (A/D Control 1)........................................ 251 AD1CON2 (A/D Control 2)........................................ 252 AD1CON3 (A/D Control 3)........................................ 253 AD1CSSH (A/D Input Scan Select, High)................. 256 AD1CSSL (A/D Input Scan Select, Low) .................. 256 AD1PCFGH (A/D Port Configuration, High) ............. 255 AD1PCFGL (A/D Port Configuration, Low)............... 255 ALCFGRPT (Alarm Configuration) ........................... 239 ALMINSEC (Alarm Minutes and Seconds Value) ................................................ 243 ALMTHDY (Alarm Month and Day Value) ................ 242 ALWDHR (Alarm Weekday and Hours Value) ......... 242 BDnSTAT Prototype (Buffer Descriptor n Status, CPU Mode) ...................... 199 BDnSTAT Prototype (Buffer Descriptor n Status, USB Mode) ...................... 198 CLKDIV (Clock Divider) ............................................ 113 CMSTAT (Comparator Status) ................................. 262 CMxCON (Comparator x Control) ............................ 261 CORCON (CPU Control) ............................................ 29 CORCON (CPU Core Control) ................................... 71 CRCCON (CRC Control) .......................................... 247 CRCXOR (CRC XOR Polynomial) ........................... 248 CTMUCON (CTMU Control)..................................... 267 CTMUICON (CTMU Current Control) ....................... 268 CVRCON (Comparator Voltage Reference Control) ........................................... 264 CW1 (Flash Configuration Word 1) .......................... 270 CW2 (Flash Configuration Word 2) .......................... 272 CW3 (Flash Configuration Word 3) .......................... 273 DEVID (Device ID).................................................... 274 DEVREV (Device Revision)...................................... 274 I2CxCON (I2Cx Control)........................................... 182 I2CxMSK (I2C Slave Mode Address Mask).............. 186 I2CxSTAT (I2Cx Status) ........................................... 184 ICxCON1 (Input Capture x Control 1)....................... 157 ICxCON2 (Input Capture x Control 2)....................... 158 IECn (Interrupt Enable Control 0-5)...................... 80-86 IFSn (Interrupt Flag Status 0-5)............................ 74-79 INTCON1 (Interrupt Control 1) ................................... 72 INTCON2 (Interrupt Control 2) ................................... 73 IPCn (Interrupt Priority Control 0-23).................. 87-107 MINSEC (RTCC Minutes and Seconds Value) ................................................ 241 MTHDY (RTCC Month and Day Value).................... 240 NVMCON (Flash Memory Control)............................. 57 OCxCON1 (Output Compare x Control 1) ................ 165 OCxCON2 (Output Compare x Control 2) ................ 166 OSCCON (Oscillator Control)................................... 111 OSCTUN (FRC Oscillator Tune) .............................. 114 PADCFG1 (Pad Configuration Control).................... 231 PADCFG1 (Pad Configuration) ................................ 238 PMADDR (PMP Address)......................................... 229 PMAEN (PMP Enable) ............................................. 229 PMMODE (Parallel Port Mode) ................................ 228 PMPCON (PMP Control) .......................................... 226 PMSTAT (PMP Status)............................................. 230 RCFGCAL (RTCC Calibration and Configuration) ................................................... 237 RCON (Reset Control)................................................ 62 REFOCON (Reference Oscillator Control) ............... 118 RPINRn (PPS Input Mapping 0-29).................. 128-138 RPORn (PPS Output Mapping 0-15)................ 138-146
R
Reader Response ............................................................. 324 Reference Clock Output.................................................... 117 Register Maps A/D Converter ............................................................. 45 Comparators ............................................................... 48 CPU Core.................................................................... 35 CRC ............................................................................ 48 CTMU.......................................................................... 45 I2C............................................................................... 41 ICN.............................................................................. 36 Input Capture .............................................................. 39 Interrupt Controller ...................................................... 37 NVM ............................................................................ 50 Output Compare ......................................................... 40 Pad Configuration ....................................................... 44 Parallel Master/Slave Port .......................................... 47 Peripheral Pin Select .................................................. 49 PMD ............................................................................ 50 PORTA........................................................................ 43 PORTB........................................................................ 43 PORTC ....................................................................... 43 PORTD ....................................................................... 43 PORTE........................................................................ 44 PORTF........................................................................ 44 PORTG ....................................................................... 44 RTCC .......................................................................... 48 SPI .............................................................................. 42 System ........................................................................ 50 Timers ......................................................................... 38 UART .......................................................................... 42 USB OTG.................................................................... 46
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SPIxCON1 (SPIx Control 1) ...................................... 174 SPIxCON2 (SPIx Control 2) ...................................... 175 SPIxSTAT (SPIx Status) ........................................... 172 SR (ALU STATUS) ............................................... 28, 71 T1CON (Timer1 Control)........................................... 148 TxCON (Timer2 and Timer4 Control)........................ 152 TyCON (Timer3 and Timer5 Control)........................ 153 U1ADDR (USB Address) .......................................... 212 U1CNFG1 (USB Configuration 1) ............................. 213 U1CNFG2 (USB Configuration 2) ............................. 214 U1CON (USB Control, Device Mode) ....................... 210 U1CON (USB Control, Host Mode)........................... 211 U1EIE (USB Error Interrupt Enable) ......................... 221 U1EIR (USB Error Interrupt Status) .......................... 220 U1EPn (USB Endpoint n Control) ............................. 222 U1IE (USB Interrupt Enable)..................................... 219 U1IR (USB Interrupt Status, Device Mode) .............. 217 U1IR (USB Interrupt Status, Host Mode) .................. 218 U1OTGCON (USB OTG Control) ............................. 207 U1OTGIE (USB OTG Interrupt Enable) .................... 216 U1OTGIR (USB OTG Interrupt Status) ..................... 215 U1OTGSTAT (USB OTG Status).............................. 206 U1PWMCON USB (VBUS PWM Generator Control) ............................................ 223 U1PWRC (USB Power Control) ................................ 208 U1SOF (USB OTG Start-Of-Token Threshold)......................................................... 213 U1STAT (USB Status) .............................................. 209 U1TOK (USB Token) ................................................ 212 UxMODE (UARTx Mode) .......................................... 190 UxSTA (UARTx Status and Control) ......................... 192 WKDYHR (RTCC Weekday and Hours Value) ..................................................... 241 YEAR (RTCC Year Value) ........................................ 240 Resets BOR (Brown-out Reset) .............................................. 61 Clock Source Selection ............................................... 63 CM (Configuration Mismatch Reset) ........................... 61 Delay Times ................................................................ 64 Device Times .............................................................. 63 IOPUWR (Illegal Opcode Reset) ................................ 61 MCLR (Pin Reset) ....................................................... 61 POR (Power-on Reset) ............................................... 61 RCON Flags Operation ............................................... 63 SFR States.................................................................. 65 SWR (RESET Instruction)........................................... 61 TRAPR (Trap Conflict Reset)...................................... 61 UWR (Uninitialized W Register Reset)........................ 61 WDT (Watchdog Timer Reset).................................... 61 Revision History ................................................................ 317 RTCC Alarm Configuration .................................................. 244 Calibration ................................................................. 243 Register Mapping ...................................................... 236
S
Selective Peripheral Power Control .................................. 120 Serial Peripheral Interface. See SPI. SFR Space ......................................................................... 34 Sleep Mode....................................................................... 119 Software Simulator (MPLAB SIM) .................................... 282 Software Stack.................................................................... 51 Special Features................................................................. 10 SPI
T
Timer1............................................................................... 147 Timer2/3 and Timer4/5 ..................................................... 149 Timing Diagrams CLKO and I/O Timing ............................................... 304 External Clock........................................................... 302
U
UART ................................................................................ 187 Baud Rate Generator (BRG) .................................... 188 Operation of UxCTS and UxRTS Pins...................... 189 Receiving .................................................................. 189 Transmitting 8-Bit Data Mode................................................ 189 9-Bit Data Mode................................................ 189 Break and Sync Sequence ............................... 189 Universal Asynchronous Receiver Transmitter. See UART. Universal Serial Bus. See USB OTG. USB On-The-Go (OTG) ...................................................... 10 USB OTG Buffer Descriptors and BDT...................................... 197 Device Mode Operation ............................................ 202 DMA Interface........................................................... 198 Host Mode Operation................................................ 202 Interrupts .................................................................. 201 OTG Operation ......................................................... 204 Registers .......................................................... 205-223 VBUS Voltage Generation ......................................... 200
V
VDDCORE/VCAP Pin ........................................................... 275 Voltage Regulator (On-Chip) ............................................ 275 and BOR ................................................................... 276 Standby Mode .......................................................... 276 Tracking Mode .......................................................... 275
W
Watchdog Timer (WDT).................................................... 276 Control Register........................................................ 277 Windowed Operation ................................................ 277 WWW Address ................................................................. 323 WWW, On-Line Support ....................................................... 7
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THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.
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READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS39897B FAX: (______) _________ - _________
Device: PIC24FJ256GB110 Family Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
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PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 FJ 256 GB1 10 T - I / PT - XXX Microchip Trademark Architecture Flash Memory Family Program Memory Size (KB) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern
b)
Examples:
a) PIC24FJ64GB106-I/PT: PIC24F device with USB On-The-Go, 64-Kbyte program memory, 64-pin, Industrial temp.,TQFP package. PIC24FJ256GB110-I/PT: PIC24F device with USB On-The-Go, 256-Kbyte program memory, 100-pin, Industrial temp.,TQFP package.
Architecture Flash Memory Family Product Group
24 FJ
= 16-bit modified Harvard without DSP = Flash program memory
GB1 = General purpose microcontrollers with USB On-The-Go 06 08 10 I PF PT = 64-pin = 80-pin = 100-pin = -40C to +85C (Industrial) = 100-lead (14x14x1 mm) TQFP (Thin Quad Flatpack) = 64-lead, 80-lead, 100-lead (12x12x1 mm) TQFP (Thin Quad Flatpack)
Pin Count
Temperature Range Package
Pattern
Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample
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WORLDWIDE SALES AND SERVICE
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01/02/08
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Price & Availability of PIC24FJ192GB

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